參數(shù)資料
型號(hào)： DDC114
英文描述： Quad Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述： 四路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 21/30頁
文件大?。?/td> 389K
代理商： DDC114
""#
SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
21
DATA FORMAT (FORMAT)
The serial output data is provided in an offset binary code
as shown in Table 9. The digital input pin FORMAT selects
how many bits are used in the output word. When
FORMAT is high (1), 20 bits are used. When FORMAT is
low (0), the lower 4 bits are truncated so that only 16 bits
are used. Note that the LSB size is 16 times bigger when
FORMAT = 0. An offset is included in the output to allow
slightly negative inputs, from board leakages for example,
from clipping the reading. This offset is approximately
0.4% of the positive fullscale.
Table 9. Ideal Output Code
(1)
vs Input Signal
INPUT
SIGNAL
IDEAL OUTPUT CODE
FORMAT = HIGH
(1)
IDEAL OUTPUT CODE
FORMAT = LOW
(0)
≥
100% FS
1111 1111 1111 1111 1111
1111 1111 1111 1111
0.001531% FS
0000 0001 0000 0001 0000
0000 0001 0000 0001
0.001436% FS
0000 0001 0000 0000 1111
0000 0001 0000 0000
0.000191% FS
0000 0001 0000 0000 0010
0000 0001 0000 0000
0.000096% FS
0000 0001 0000 0000 0001
0000 0001 0000 0000
0% FS
0000 0001 0000 0000 0000
0000 0001 0000 0000
0.3955% FS
(1)Excludes the effects of noise, INL, offset, and gain errors.
0000 0000 0000 0000 0000
0000 0000 0000 0000
DATA RETRIEVAL
In both the continuous and non-continuous modes of
operation, the data from the last conversion is available for
retrieval on the falling edge of DVALID (see Figure 21 and
Table 10, on page 22). Data is shifted out of the falling
edge of the data clock, DCLK. Make sure not to retrieve
data around while CONV changes as this can introduce
noise. Stop activity on DCLK at least 10
μ
s before or after
a CONV transition.
Setting the FORMAT pin = 0 (16-bit output word) will
reduce the time needed to retrieve data by 20% since there
are fewer bits to shift out. This can be useful in
multichannel systems requiring only 16 bits of resolution.
相關(guān)PDF資料
PDF描述
DDC114TH-7 NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
DDC114EK NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DDC114EH 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
DDC114EH-7 功能描述:開關(guān)晶體管 - 偏壓電阻器 150MW 10K RoHS:否 制造商:ON Semiconductor 配置: 晶體管極性:NPN/PNP 典型輸入電阻器: 典型電阻器比率: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 直流集電極/Base Gain hfe Min:200 mA 最大工作頻率: 集電極—發(fā)射極最大電壓 VCEO:50 V 集電極連續(xù)電流:150 mA 峰值直流集電極電流: 功率耗散:200 mW 最大工作溫度: 封裝:Reel
DDC114EH-7-F 制造商:Diodes Incorporated 功能描述:TRANS DGTL BJT NPN 100MA 6PIN SOT-563 - Tape and Reel
DDC114EK 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
DDC114EK-7 制造商:Diodes Incorporated 功能描述:TRANS DGTL BJT NPN 100MA 6PIN SOT-26 - Tape and Reel
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