4
Data Device Corporation
www.ddc-web.com
DD-00429
ciated Txn Parity bit in the ARINC Control Register 1.This is use-
ful to verify proper operation of the parity check circuitry for each
of the receive circuits during wraparound test mode.
PROCESSOR INTERFACE
The processor interface allows for the use of either an 8- or 16-bit
data bus. Intel or Motorola control signal formats can also be used.
INTERRUPT OPERATIONAL MODES
The DD-00429 provides four interrupt outputs. Three of these
interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose
programmable interrupts.The fourth interrupt is an Error interrupt
output which is specifically used to provide indications of various
error conditions and is nonmaskable.
ERROR INTERRUPT OPERATION
When an error condition occurs, the ERROR output pin goes low
to indicate the presence of an error. The error pin will go high
again when the Error Status Register is clear. Each of these bits
is cleared by either reading the Error Status Register or remov-
ing the error condition.
GENERAL PURPOSE INTERRUPTS
The three general purpose interrupt outputs can be used for mul-
tilevel interrupts or to trigger other external hardware for various
conditions. Each condition can be mapped to any one of the
three general purpose interrupts or disabled (by mapping to
IRQ0 which does not exist). Each interrupt output can be pro-
grammed to be either a LEVEL interrupt or PULSE interrupt via
TABLE 3. DD-00429VP (144-PIN TQFP) ASIC PINOUTS
DESCRIPTION
PIN NO.
DESCRIPTION
+5V
TX DB11
TX DB12
TX DB13
TX DB14
TX DB15
EN RX1
EN RX0
SELECT
RX RDY1
RX RDY0
GND
GND
GND
INT/ MOTO
8/16
+5V
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS0
CS1
CS2
BIST R3 (N/C)
GND
+5V
GND
PIN NO.
PIN NO.
DESCRIPTION
PIN NO.
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
+5V
XTAL1 (N/C)
GND
TSB2 (N/C)
TSB3 (N/C)
TSA0 (N/C)
TSA1 (N/C)
TSA2 (N/C)
TSA3 (N/C)
TMA0 (N/C)
TMA1 (N/C)
TMA2 (N/C)
TMA3 (N/C)
TMA4 (N/C)
TMA5 (N/C)
TMA6 (N/C)
TMA7 (N/C)
TSB0 (N/C)
TSB1 (N/C)
+5V
GND
TMB4 (N/C)
TMB5 (N/C)
TMB6 (N/C)
TMB7 (N/C)
ZERO WAIT MODE
READY
RD or DS
WR or RD/WR
DTACK
ERROR
MASTER RESET
+5V
BIST TOA (N/C)
BIST TOB (N/C)
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
+5V
OSC CLK OUT (N/C)
BIST DMT (N/C)
BIST RAM 7 (N/C)
BIST RAM 24 (N/C)
D0
D1
D2
D3
D4
D5
D6
D7
GND
+5V
GND
+5V
D8
D9
D10
D11
D12
D13
D14
D15
GND
GND
IRQ3
IRQ2
IRQ1
RESET RC
ARINC CLK OUT
ARINC CLK 1
ARINC CLK 0
BIST R2 (N/C)
GND
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
+5V
RESET 1
CW STRB1
EN TX1 OUT
TX1 EMPTY
LD TX1 HI
LD TX1 LOW
+5V
GND
+5V
16 MHZ CLOCK
EN RX3
EN RX2
RX RDY3
RX RDY2
+5V
GND
RESET 0
CW STRB 0
EN TX0 OUT
TX0 EMPTY
LD TX0 HI
LD TX0 LOW
GND
TX DB0
TX DB1
TX DB2
TX DB3
TX DB4
TX DB5
TX DB6
TX DB7
TX DB8
TX DB9
TX DB10
GND