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參數(shù)資料
| 型號： | DD00429FP-900 |
| 英文描述： | MIL-STD-1553/ARINC BUS CONTROLLER/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 101K |
| 代理商： | DD00429FP-900 |
DD-00429
ARINC 429 MICROPROCESSOR INTERFACE
DESCRIPTION
DDC's DD-00429 provides a complete and
flexible interface between a microproces-
sor and an ARINC 429 data bus.The DD-
00429 interfaces to a processor through a
128 x 32 bit static RAM as well as four 32
x 32 receive FIFOs and two 32 x 32 trans-
mit FIFOs. The DD-00429 can be easily
interfaced to 8- or 16-bit processors via a
buffered shared RAM configuration.
The DD-00429, when configured with two
DD-03282 Transceivers, supports four
ARINC 429 Receive channels (Rx0, Rx1,
Rx2 and Rx3) each receiving data inde-
pendently. The receive data rates (high or
low speed) for channel Rx0 and Rx1 can
be programmed independently from Rx2
and Rx3. The DD-00429 can decode and
sort data based on the ARINC 429 Label
and SDI bits via the Data Match Processor
and store it in RAM and/or FIFOs via the
Data Store Processor.
The DD-00429, when configured with
two DD-03182 Line Drivers, supports
two ARINC 429 Transmit channels (Tx0
and Tx1) and can transmit data indepen-
dently.The transmit data rate can also be
programmed independently. There are
two 32 x 32 bit FIFOs for each of the
transmitters that send out data.
The DD-00429 has the capability of pro-
gramming three general purpose inter-
rupts as well as generating an interrupt
based on an error condition. The general
purpose interrupts can be programmed to
trigger other external hardware.They can
either be LEVEL or PULSE triggered.
The features built into the DD-00429
enable the user to off-load the host
processor and use that processing time
to implement operations other than
polling the ARINC 429 Bus. The decod-
ing and sorting of data allows the user to
gather data much quicker than past
designs. If the user requires a micro-
processor in the avionics box, this device
will facilitate a clean and quick design.
FEATURES
Four ARINC 429 Receive
Channels, (configured with
DD-03282 Transceivers)
128 x 32 Shared RAM Interface
Label and Destination
Decoding and Sorting
Two ARINC 429 Transmit
Channels (configured with
DD-03182 Line Drivers)
Two 32 x 32 Transmit FIFO's
Interfaces Easily to 8- or 16-Bit
Microprocessor
Built-in Fault Detection
Circuitry
Free “C” Library Software
Application Note AN/A-6
“FAQ’s”
ARINC 429
ARINC 429
Rx1 LOGIC
ARINC 429
Rx2 LOGIC
ARINC 429
ARINC 429
Tx0 LOGIC
ARINC 429
Tx1 LOGIC
Tx FIFO
32 WORDS
Tx FIFO
Rx0 FIFO
32 WORDS
Rx1 FIFO
Rx2 FIFO
32 WORDS
Rx3 FIFO
32 WORDS
ARINC 429
ARINC 429
ARINC 429
ARINC 429
ARINC 429
ARINC 429
2
2
WRAPAROUND
Rx DATA
DATA
MATCH
PROCESSOR
DATA
ADDR
CTRL
DATA
ADDR
128 X 16
STATIC RAM
DMT RAM
CTRL DATA
ADDR
128 X 32
STATIC RAM
Rx RAM
DATA
STORE
PROCESSOR
DATA
ADDR
DMP
DATA
ADDR
ADDR
DATA
DATA
INTERRUPT
CONTROLLER
3
16
12
IRQ
DATA
ADDR
CONTROL
MICROPROCESSOR
OR CPU
DD-00429VP ASIC
CPU INTERFACE
DATA
DD-03282 TRANSCEIVER (2)
WRAPAROUND
WRAPAROUND
WRAPAROUND
DD-03182 LINE DRIVER (2)
DD-03182
LINE
DRIVER
DD-03182
LINE
DRIVER
A2
OUT
A1
OUT
B2
OUT
B1
OUT
1998, 1999 Data Device Corporation
FIGURE 1. CHIP SET BLOCK DIAGRAM
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