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參數(shù)資料
| 型號(hào)： | DC847A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 28/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2446 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC847A Design File DC847A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2446 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2446CUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446CUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN |
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LTC2446/LTC2447
9
24467fa
convert the bipolar differential input signal, VIN = IN+ –
IN– (where IN+ and IN– are the selected input channels),
from – FS = – 0.5 VREF to +FS = 0.5 VREF where VREF =
REF+ – REF– (REF+ and REF– are the selected references).
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes.
MUXOUT/ADCIN
There are two differences between the LTC2446 and the
LTC2447. The first is the RMS noise performance. For a
given OSR, the LTC2447 noise level is approximately
√2
times lower (0.5 effective bits)than that of the LTC2446.
The second difference is the LTC2447 includes MUXOUT/
ADCIN pins. These pins enable an external buffer or gain
block to be inserted between the selected input channel of
the multiplexer and the input to the ADC. Since the buffer
is driven by the output of the multiplexer, only one circuit
is required for all 8 input channels. Additionally, the
transparent calibration feature of the LTC244X family
automatically removes the offset errors of the external
buffer.
In order to achieve optimum performance, the MUXOUT
and ADCIN pins should not be shorted together. In appli-
cations where the MUXOUT and ADCIN need to be shorted
together, the LTC2446 should be used because the
MUXOUT and ADCIN are internally connected for opti-
mum performance.
Output Data Format
The LTC2446/LTC2447 serial output data stream is 32 bits
long. The first 3 bits represent status information indicat-
ing the sign and conversion state. The next 24 bits are the
conversion result, MSB first. The remaining 5 bits are sub
LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effective
bits of performance are possible (see Table 4). Under
these conditions, sub LSBs are included in the conversion
result and represent useful information beyond the 24-bit
level. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2446/LTC2447 Status Bits
BIT 31
BIT 30
BIT 29
BIT 28
INPUT RANGE
EOC
DMY
SIG
MSB
VIN ≥ 0.5 VREF
0011
0V
≤ VIN < 0.5 VREF
0010
–0.5 VREF ≤ VIN < 0V
0001
VIN < – 0.5 VREF
0000
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
APPLICATIO S I FOR ATIO
WU
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