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參數(shù)資料
| 型號(hào)： | DC847A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2446 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC847A Design File DC847A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2446 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2446CUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446CUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN |
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LTC2446/LTC2447
8
24467fa
sleep state. While in this sleep state, power consumption
is reduced below 10
A. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result while operating in the 1x mode. The data output cor-
responds to the conversion just performed. This result is
shifted out on the serial data out pin (SDO) under the con-
trol of the serial clock (SCK). Data is updated on the falling
edge of SCK allowing the user to reliably latch data on the
rising edge of SCK (see Figure 3). The data output state is
concluded once 32 bits are read out of the ADC or when CS
is brought HIGH. The device automatically initiates a new
conversion and the cycle repeats.
Through timing control of the CS, SCK and EXT pins, the
LTC2446/LTC2447 offer several flexible modes of opera-
tion (internal or external SCK). These various modes do
not require programming configuration registers; more-
over, they do not disturb the cyclic operation described
above. These modes of operation are described in detail in
the Serial Interface Timing Modes section.
Ease of Use
The LTC2446/LTC2447 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle while operating in the 1x mode. There
is a one-to-one correspondence between the conversion
and the output data. Therefore, multiplexing multiple
analog voltages and references is easy. Speed/resolution
adjustments may be made seamlessly between two
conversions without settling errors.
The LTC2446/LTC2447 perform offset and full-scale cali-
brations every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2446/LTC2447 automatically enter an internal
reset state when the power supply voltage VCC drops
APPLICATIO S I FOR ATIO
WU
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below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial inter-
face mode selection.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. The conversion imme-
diately following a POR is performed on the input channel
IN+ = CH0, IN– = CH1, REF+ = VREF01+, REF– VREF01– at an
OSR = 256 in the 1x mode. Following the POR signal, the
LTC2446/LTC2447 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (4.5V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
These converters accept truly differential external refer-
ence voltages. Each set of five reference inputs may be
independently driven to any common mode voltage over
the entire supply range of the device (GND to VCC). For
correct converter operation, each positive reference pin
REF+ (VREF01+, VREF23+, VREF45+, VREF67+, VREFG+) must
be more positive than its corresponding negative refer-
ence pin REF– (VREF01–, VREF23–, VREF45–, VREF67–,
VREFG–) by at least 100mV.
The LTC2446/LTC2447 can accept a differential reference
from 0.1V to VCC on each set of reference input pins. The
converter output noise is determined by the thermal noise
of the front-end circuits, and as such, its value in micro-
volts is nearly constant with reference voltage. A decrease
in reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a
reduced reference voltage will improve the converter’s
overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0-CH7 and COM input
pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2446/LTC2447
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