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參數(shù)資料
| 型號： | DC586A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2431 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC586A Design File DC586A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2431 |
| 已供物品： | 板 |
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LTC2430/LTC2431
13
24301f
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2430/LTC2431 Status Bits
Bit 23
Bit 22 Bit 21 Bit 20
Input Range
EOC
DMY
SIG
MSB
VIN ≥ 0.5 VREF
00
1
0V
≤ VIN < 0.5 VREF
00
1
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < – 0.5 VREF
00
0
Bits 20-0 are the 21-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 22) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN+ and IN– pins is maintained
within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = – 0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater than
Table 2. LTC2430/LTC2431 Output Data Format
Differential Input Voltage
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
…
Bit 0
VIN*
EOC
DMY
SIG
MSB
LSB
VIN* ≥ 0.5 VREF**
0
0110
0
…
0
0.5 VREF** – 1LSB
0
0101
1
…
1
0.25 VREF**
0
0101
0
…
0
0.25 VREF** – 1LSB
0
0100
1
…
1
0
0100
0
…
0
–1LSB
0
0011
1
…
1
– 0.25 VREF**
0
0011
0
…
0
– 0.25 VREF** – 1LSB
0
0010
1
…
1
– 0.5 VREF**
0
0010
0
…
0
VIN* < –0.5 VREF**
0
0001
1
…
1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
Figure 3. Output Data Timing
MSB
SIG
“0”
12
3
4
5
24
BIT 0
LSB
BIT 19
BIT 20
BIT 21
BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2431 F03
Hi-Z
APPLICATIO S I FOR ATIO
WU
UU
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