參數(shù)資料
型號(hào)： DC571A
廠商： Linear Technology
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2418
軟件下載： QuikEval System
設(shè)計(jì)資源： DC571A Design File
DC571A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2418
已供物品： 板
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LTC2414/LTC2418
23
241418fa
Whenever SCK is LOW, the LTC2414/LTC2418’s internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2414/LTC2418’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK timing
mode. By adding an external 10k pull-up resistor to SCK,
this pin goes HIGH once the external driver goes Hi-Z. On
the next CS falling edge, the device will remain in the in-
ternal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 10. CS may be perma-
nently tied to ground, simplifying the user interface or
isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
APPLICATIO S I FOR ATIO
WU
UU
Figure 9. Internal Serial Clock, Reduced Data Output Length
(1)
(0)
EN
SGL
A2
A1
A0
ODD/
SIGN
SDI
DON’T CARE
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSB
SIG
BIT 8
TEST EOC
(OPTIONAL)
TEST EOC
BIT 27
BIT 26
BIT 25
BIT 24
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP
DATA OUTPUT
Hi-Z
DATA
OUTPUT
CONVERSION
SLEEP
2411 F09
<tEOCtest
VCC
10k
TEST EOC
VCC
FO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
919
11
12
21
28
1
8
10
18
17
15
16
20
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
1
F
2.7V TO 5.5V
LTC2414/
LTC2418
4-WIRE
SPI INTERFACE
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