LTC2752
2752f
500ns/DIV
UPD
5V/DIV
GATED
SETTLING
WAVEFORM
100V/DIV
(AVERAGED)
2752 G14
LT1468 AMP; CFEEDBACK = 20pF
0V TO 10V STEP
VREF = –10V; SPAN CODE = 0000
tSETTLE = 1.7s to 0.0015% (16 BITS)
Typical perForMance characTerisTics
VDD (V)
2.5
0.5
LOGIC
THRESHOLD
(V)
0.75
1
1.25
1.5
2
3
3.5
4
4.5
5
5.5
1.75
2752 G12
RISING
FALLING
Logic Threshold
vs Supply Voltage
Supply Current
vs Logic Input Voltage
Supply Current
vs Clock Frequency
Midscale Glitch (VDD = 3V)
Settling Full-Scale Step
DIGITAL INPUT VOLTAGE (V)
0
SUPPL
YCURRENT
(mA)
3
4
5
4
2752 G11
2
1
0
1
2
3
5
VDD = 5V
CLR, LDAC, SDI, SCK,
CS/LD TIED TOGETHER
VDD = 3V
SCK FREQUENCY (Hz)
1
0.0001
SUPPL
YCURRENT
(mA)
0.001
0.01
0.1
1
10
100
VDD = 5V
100
10k
1M
100M
2752 G13
VDD = 3V
ALTERNATING ZERO
AND FULL-SCALE
Midscale Glitch (VDD = 5V)
500ns/DIV
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
2752 G15
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
FALLING MAJOR CARRY TRANSITION.
RISING TRANSITION IS SIMILAR OR BETTER.
0.6nVs TYP
500ns/DIV
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
2752 G16
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
FALLING MAJOR CARRY TRANSITION.
RISING TRANSITION IS SIMILAR OR BETTER.
2.2nVs TYP
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.