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參數(shù)資料
| 型號： | DC1562A-L |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/26頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LTC6994-2 |
| 設(shè)計(jì)資源： | DC1562A Design Files DC1562A Schematic |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 主要目的： | 定時(shí)，延遲線路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC6994-2 |
| 主要屬性： | 100ms 下降沿與上升沿延遲 |
| 次要屬性： | 2.25 V ~ 5.5 V 電源 |
| 已供物品： | 板 |
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LTC6994-1/LTC6994-2
12
699412fb
operaTion
Table 1. DIVCODE Programming
DIVCODE
POL
NDIV
Recommended tDELAY
R1 (k)
R2 (k)
VDIV/V+
0
1
1s to 16s
Open
Short
≤ 0.03125 ±0.015
1
0
8
8s to 128s
976
102
0.09375 ±0.015
2
0
64
64s to 1.024ms
976
182
0.15625 ±0.015
3
0
512
512s to 8.192ms
1000
280
0.21875 ±0.015
4
0
4,096
4.096ms to 65.54ms
1000
392
0.28125 ±0.015
5
0
32,768
32.77ms to 524.3ms
1000
523
0.34375 ±0.015
6
0
262,144
262.1ms to 4.194sec
1000
681
0.40625 ±0.015
7
0
2,097,152
2.097sec to 33.55sec
1000
887
0.46875 ±0.015
8
1
2,097,152
2.097sec to 33.55sec
887
1000
0.53125 ±0.015
9
1
262,144
262.1ms to 4.194sec
681
1000
0.59375 ±0.015
10
1
32,768
32.77ms to 524.3ms
523
1000
0.65625 ±0.015
11
1
4,096
4.096ms to 65.54ms
392
1000
0.71875 ±0.015
12
1
512
512s to 8.192ms
280
1000
0.78125 ±0.015
13
1
64
64s to 1.024ms
182
976
0.84375 ±0.015
14
1
8
8s to 128s
102
976
0.90625 ±0.015
15
1
1s to 16s
Short
Open
≥ 0.96875 ±0.015
Figure 2. Delay Range and POL Bit vs DIVCODE
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+
=
DIVCODE
+ 0.5
16
±1.5%
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
is 4, VDIV = 0.281 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
0.5V+
t DELA
Y(ms)
699412 F02
1000
10000
100
10
1
0.001
0.1
0.01
INCREASING VDIV
V+
0V
POL BIT = 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
POL BIT = 1
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