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參數(shù)資料
| 型號： | DC1562A-L |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/26頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LTC6994-2 |
| 設計資源： | DC1562A Design Files DC1562A Schematic |
| 特色產(chǎn)品： | TimerBlox? |
| 標準包裝： | 1 |
| 系列： | TimerBlox® |
| 主要目的： | 定時，延遲線路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC6994-2 |
| 主要屬性： | 100ms 下降沿與上升沿延遲 |
| 次要屬性： | 2.25 V ~ 5.5 V 電源 |
| 已供物品： | 板 |
LTC6994-1/LTC6994-2
19
699412fb
Power Supply Current
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting for an input transi-
tion). IS(IDLE) varies with the programmed tDELAY and the
supply voltage, as described by the equations in Table 2,
valid for both the LTC6994-1 and LTC6994-2.
Table 2. Approximate Idle Supply Current Equations
CONDITION
TYPICAL IS(IDLE)
NDIV ≤ 64
V+ NDIV 7pF + 4pF
(
)
tDELAY
+
V+
500k
+ 2.2ISET +50A
NDIV ≥ 512
V+ NDIV 7pF
tDELAY
+
V+
500k
+1.8 ISET +50A
When an input transition starts the delay timing circuity,
the instantaneous supply current increases to IS(ACTIVE).
IS(ACTIVE) = IS(IDLE) + IS(ACTIVE)
applicaTions inForMaTion
IS(ACTIVE)canbeestimatedusingtheequationsinTable 3,
assuming a periodic input with frequency fIN. The equa-
tions assume the input pulse width is greater than tDELAY;
otherwise, the output will not transition (and the increase
in supply current will be less).
Table 3. Active Increase in Supply Current
CONDITION
DEVICE
TYPICAL IS(ACTIVE)*
NDIV ≤ 64
LTC6994-1
fIN V+ (NDIV 5pF + 18pF + CLOAD)
LTC6994-2
fIN V+ (NDIV 10pF + 22pF + CLOAD)
NDIV ≥ 512 Either Version
fIN V+ CLOAD
*Ignoring resistive loads (assumes RLOAD = ∞)
Figures 14 and 15 show how the supply current increases
from IS(IDLE) as the input frequency increases. At higher
NDIV settings, the increase in active current is smaller.
fIN tDELAY
“IDLE”
POWER
SUPPL
YCURRENT
(A)
150
200
250
0.8
699412 F14
100
50
0
0.2
0.4
0.6
1.0
÷1, RSET = 50k
÷8, RSET = 50k
÷1, RSET = 100k
÷1, RSET = 800k
V+ = 3.3V
INPUT PULSE WIDTH = 1.1 tDELAY
CLOAD = 5pF
RLOAD = ∞
fIN tDELAY
“IDLE”
POWER
SUPPL
YCURRENT
(A)
150
200
250
0.4
699412 F15
100
50
0
0.1
0.2
0.3
0.5
÷1, RSET = 50k
÷8, RSET = 50k
÷1, RSET = 100k
÷1, RSET = 800k
V+ = 3.3V
fIN < 1/(2 tDELAY) TO ALLOW RISING AND
FALLING DELAYS TO REACH THE OUTPUT
CLOAD = 5pF
RLOAD = ∞
Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1
Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2
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