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參數資料
| 型號： | DC1444A-B |
| 廠商： | Linear Technology |
| 文件頁數： | 26/26頁 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2305 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC1444A Design File DC1444A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數量： | 2 |
| 位數： | 12 |
| 采樣率（每秒）： | 14k |
| 數據接口： | I²C，串行 |
| 在以下條件下的電源（標準）： | 1.5mW @ 1kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2305 |
| 已供物品： | 板 |
| 相關產品： | LTC2305IMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305IDE#TRPBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305IDE#PBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305HMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305HMS#PBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CMS#PBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CDE#TRPBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305CDE#PBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305IMS#PBF-ND - IC ADC 12BIT I2C 12-MSOP |
LTC2301/LTC2305
9
23015fb
PIN FUNCTIONS
GND (Pins 1, 4, 9): Ground. All GND pins must be con-
nected to a solid ground plane.
SDA (Pin 2): Bidirectional Serial Data Line of the I2C In-
terface. In transmitter mode (read), the conversion result
is output at the SDA pin, while in receiver mode (write),
the DIN word is input at the SDA pin to congure the ADC.
The pin is high impedance during the data input mode and
is an open drain output (requires an appropriate pull-up
device to VDD) during the data output mode.
SCL (Pin 3): Serial Clock Pin of the I2C Interface. The
LTC2301 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
IN+, IN– (Pins 5, 6):
Positive (IN+) and negative (IN–)
differential analog inputs.
VREF (Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2μF ceramic capacitor. The internal refer-
ence may be overdriven by an external 2.5V reference at
this pin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with 10μF and 0.1μF ceramic capacitors in parallel.
Nominal output voltage is 4.096V. The internal reference
buffer driving this pin is disabled by grounding VREF, al-
lowing REFCOMP to be overdriven by an external source
(see Figure 5c).
VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V
to 5.25V. Bypass VDD to GND with 10μF and 0.1μF ceramic
capacitors in parallel.
AD1 (Pin 11): Chip Address Control Pin. This pin is con-
gured as a three-state (LOW, HIGH, oating) address
control bit for the device I2C address. See Table 2 for
address selection.
AD0 (Pin 12): Chip Address Control Pin. This pin is con-
gured as a three-state (LOW, HIGH, oating) address
control bit for the device I2C address. See Table 2 for
address selection.
GND (Pin 13 – DFN Package Only): Exposed Pad Ground.
Must be soldered directly to ground plane.
(LTC2301)
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