參數(shù)資料
型號(hào): DAC8571IDGKR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 13 us SETTLING TIME, 16-BIT DAC, PDSO8
封裝: GREEN, PLASTIC, MSOP-8
文件頁(yè)數(shù): 29/30頁(yè)
文件大?。?/td> 825K
代理商: DAC8571IDGKR
www.ti.com
0
500
1000
1500
2000
2500
0
40
80
120
160
200
240
280
IDD - Supply Current - A
f-
F
requency
IREF Included
VDD = 2.7 V
VDD = 5.5 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
1
2
3
4
5
Logic Input Voltage - V
I DD
-
Supply
Curr
ent
-
mA
TA = 25°C, A0 Input (All Other Inputs = GND)
Reference Current Included
VDD = VREF = 2.7 V
VDD = VREF = 5.5 V
t - Time - 5
s/div
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
OUT
-
Output
V
oltage
-
V
2.3
2.35
2.4
2.45
2.5
0
5
10
15
20
25
30
V O
(V
,50
mV/div)
t - Time -
S
Vref = VDD - 50 mV
Code 7FFFh to 8000h
(Glitch Occurs Every N x 4096
Code Boundary)
0
1
2
3
4
5
6
t – Time – 12
s/div, Fast–Settling Mode
V
O
U
T
Output
V
oltage
V
VDD = VREF
= 5 V
Output
Loaded With
2 k
and
200 pF to
GND
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003
0.004
0.005
0
10000 20000 30000 40000 50000 60000
Digital Input Code
T
otal
Unadjusted
Error
-
V
VDD = 5 V
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
TYPICAL CHARACTERISTICS (continued)
At T
A = +25°C, unless otherwise noted.
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
HISTOGRAM OF CURRENT CONSUMPTION
Figure 13.
Figure 14.
EXITING POWER-DOWN MODE
OUTPUT GLITCH (Mid-Scale)
Figure 15.
Figure 16.
ABSOLUTE ERROR
FULL-SCALE SETTLING TIME (Large Signal)
Figure 17.
Figure 18.
8
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