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參數(shù)資料
| 型號： | DAC8562FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete 12-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 636K |
| 代理商： | DAC8562FP |
DAC8562
REV. A
–6–
As with any analog system, it is recommended that the
DAC8562 power supply be bypassed on the same PC card that
contains the chip. Figure 10 shows the power supply rejection
versus frequency performance. This should be taken into ac-
count when using higher frequency switched-mode power sup-
plies with ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
DAC8562 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the
DAC8562 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 11, pro-
vides information for operation below V
DD
= +4.75 V.
TIMING AND CONTROL
The DAC8562 has a 12-bit DAC register that simplifies inter-
face to a 12-bit (or wider) data bus. The latch is controlled by
the Chip Enable (
CE
) input. If the application does not involve
a data bus, wiring
CE
low allows direct operation of the DAC.
The data latch is level triggered and acquires data from the data
bus during the time period when
CE
is low. When
CE
goes
high, the data is latched into the register and held until
CE
re-
turns low. The minimum time required for the data to be
present on the bus before
CE
returns high is called the data
setup time (t
DS
) as seen in Figure 2. The data hold time (t
DH
) is
the amount of time that the data has to remain on the bus after
CE
goes high. The high speed timing offered by the DAC8562
provides for direct interface with no wait states in all but the
fastest microprocessors.
Typical Performance Characteristics
5
2
0
10
100
LOAD RESISTANCE –
100k
10k
1k
1
3
4
O
RL TIED TO AGND
D = FFFH
DATA = FFFH
V
DD
= +5V
T
A
= +25
°
C
R
TIED TO +5V
DATA = 000H
Figure 5. Output Swing vs. Load
TIME = 1ms/DIV
10
90
100
0%
50mV
1ms
T
A
= 25°C
NBW = 630kHz
O
Figure 8. Broadband Noise
1
10
1000
100
100
1
0.01
0.1
10
OUTPUT SINK CURRENT – μA
Figure 6. Pull-Down Voltage vs.
Output Sink Current Capability
O
V
DD
= +5V
DATA = 000H
T
A
= +85
°
C
T
A
= –40
°
C
T
A
= +25
°
C
5
0
5
1
0
3
2
4
3
2
4
1
LOGIC VOLTAGE VALUE – Volts
S
V
DD
= +5V
T
A
= +25
°
C
Figure 9. Supply Current vs. Logic
Input Voltage
80
–100
–60
–80
1
–20
–40
0
20
40
60
3
2
OUTPUT VOLTAGE – Volts
Figure 7. I
OUT
vs. V
OUT
O
POS
0
CURRENT
0
LIMIT
0
NEG
CURRENT
LIMIT
DATA = 800H
R
L
TIED TO +2V
100
0
10
100
100k
10k
1k
60
80
20
40
P
FREQUENCY – Hz
V
DD
= +5V ±200mV AC
T
A
= +25
°
C
DATA = FFFH
Figure 10. Power Supply Rejection
vs. Frequency
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