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參數(shù)資料
| 型號： | DAC8562FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete 12-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 636K |
| 代理商： | DAC8562FP |
WAFER TEST LIMITS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Reference Output Voltage
INL
DNL
V
ZSE
V
FS
V
REF
–1
–1
±
3/4
±
3/4
+1/2
4.095
2.500
+1
+ 1
+3
4.105
2.510
LSB
LSB
LSB
V
V
No Missing Codes
Data = 000
H
Data = FFF
H
4.085
2.490
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
V
IL
V
IH
I
IL
0.8
V
V
μ
A
2.4
10
SUPPLY CHARACTERISTICS
Positive Supply Current
I
DD
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5 V
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5 V
V
DD
=
±
5%
3
0.6
15
3
0.002
6
1
30
5
0.004
mA
mA
mW
mW
%/%
Power Dissipation
P
DISS
Power Supply Sensitivity
PSS
NOTE
1
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic
fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be
discharged to the destination socket before devices are inserted.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND and AGND . . . . . . . . . . . . . . . . –0.3 V, +10 V
Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V
DD
+ 0.3 V
V
REFOUT
to AGND . . . . . . . . . . . . . . . . . .–0.3 V, V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . .(T
J
max – T
A
)/
u
JA
Thermal Resistance
u
JA
20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 74
°
C/W
20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 89
°
C/W
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150
°
C
Operating Temperature Range . . . . . . . . . . . . .–40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . .–65
°
C to +150
°
C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
0
0
0
1
1
FS
ZS
DB
11–0
V
OUT
t
CEW
t
DS
t
DH
DATA VALID
t
CLRW
t
S
t
S
±1 LSB
ERROR BAND
CE
CLR
Figure 2. Timing Diagram
Table I. Control Logic Truth Table
CE
CLR
DAC Register Function
H
L
↑
+
X
H
H
H
H
L
↑
+
Latched
Transparent
Latched with New Data
Loaded with All Zeros
Latched All Zeros
↑
+ Positive Logic Transition; X Don't Care.
REV. A
–3–
(@ V
DD
= +5.0 V
6
5%, R
L
= No Load, T
A
= +25
8
C, applies to part number DAC8562GBC only,
unless otherwise noted)
DAC8562
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