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參數(shù)資料
| 型號(hào)： | DAC8512FPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V COMPLETE 8-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
DAC8512
–17–
REV. A
CLR
LD
SCLK
SCI
DAC8512
1
7
8
6
5
3
4
R1
200k
P1
10k
20mA
ADJUST
R3
80.6k
D1
R2
976k
P2
50
4mA
ADJUST
R4
54.9k
R5
100k
R6
150
Q1
2N1711
REF02
6
2
4
4–20mA
OP90
3
2
7
6
4
R7
100
ILQ-1
CLK
SCLK
+5V
10k
360
REPEAT FOR SDI, LD, & CLR
D1 = HP5082-2810
R
L
100
V
LOOP
+12 TO +40V
Figure 41. An Isolated, Programmable, 4-20 mA Process Controller
For the values shown in Figure 41,
IOUT = 3.9
A × Digital Code + 4 mA
giving a full-scale output current of 20 mA when the
DAC8512’s digital code equals FFFH. Offset trim at 4 mA is
provided by P2, and P1 provides the circuit’s gain trim at 20 mA.
These two trims do not interact because the noninverting input
of the OP90 is at virtual ground. The Schottky diode, D1, is re-
quired in this circuit to prevent loop supply power-on transients
from pulling the noninverting input of the OP90 more than
300 mV below its inverting input. Without this diode, such tran-
sients could cause phase reversal of the OP90 and possible
latchup of the controller. The loop supply voltage compliance of
the circuit is limited by the maximum applied input voltage to
the REF02 and is from +12 V to +40 V.
MICROPROCESSOR INTERFACING
DAC8512–MC68HC11 Interface
The circuit illustrated in Figure 42 shows a serial interface be-
tween the DAC8512 and the MC68HC11 8-bit microcontrol-
ler. SCK of the 68HC11 drives SCLK of the DAC8512, while
the MOSI output drives the serial data line, SDI, of the
DAC8512. The DAC’s CLR, LD, and CS signals are derived
from port lines PC1, PD5, and PC0, respectively, as shown.
For correct operation of the serial interface, the 68HC11 should
be configured such that its CPOL bit is set to 1 and its CPHA
bit is also set to 1. When the serial data is to be transmitted to
the DAC, PC0 is taken low, asserting the DAC’s CS input.
When the 68HC11 is configured in this manner, serial data on
PC1
PC0
SCK
MOSI
SS
CLK
SDI
LD
MC68HC11*
DAC8512*
CS
CLR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. DAC8512–MC68HC11 Interface
MOSI is valid on the rising edge of SCLK. The 68HC11 trans-
mits its serial data in 8-bit bytes (MSB first), with only eight ris-
ing clock edges occurring in the transmit cycle. To load data to
the DAC8512’s input serial register, PC0 is left low after the
first eight bits are transferred, and a second byte of data is then
transferred serially to the DAC8512. During the second byte
load, the first four most significant bits of the first byte are
pushed out of the DAC’s input shift register. At the end of the
second byte load, PC0 is then taken high. To prevent an acci-
dental advancing of the internal shift register, SCLK must al-
ready be asserted before PC0 is taken high. To transfer the
contents of the input shift register to the DAC register, PD5 is
taken low, asserting the DAC’s LD input. The DAC’s CLR in-
put, controlled by the 68HC11’s PC1 port, provides an asyn-
chronous clear function, setting the DAC output to zero.
Included in this section is the source code for operating the
DAC8512—M68HC11 interface.
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