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參數(shù)資料
| 型號： | DAC8426FS |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD W/V-REF 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 3µs |
| 位數(shù)： | 8 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 333k |
DAC8426
–4–
REV. C
DICE CHARACTERISTICS
DIE SIZE 0.129
× 0.152 inch, 19,608 sq. mils
(3.28
× 3.86 mm, 12.65 sq. mm)
1. VOUT B
11. DB3
2. VOUT A
12. DB2
3. VSS
13. DB1
4. VREF OUT
14. DB0 (LSB)
5. AGND
15.
WR
6. DGND
16. A1
7. DB7 (MSB)
17. A0
8. DB6
18. VDD
9. DB5
19. VOUT D
10. DB4
20. VOUT C
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8426 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DAC8426GBC
Parameter
Symbol
Conditions
Limits
Units
Total Unadjusted Error
TUE
±2
LSB max
Relative Accuracy
INL
±1
LSB max
Differential Nonlinearity
DNL
±1
LSB max
Full-Scale Error
GFSE
±1
LSB max
Zero Code Error
VZSE
±20
mV max
DAC Output Current
IOUTSOURCE
Digital In = All Ones
10
mA min
Reference Output Voltage
VREFOUT
No Load
10.04
V max
Load Regulation
LDREG
I
L = 5 mA
0.1
%/mA max
Line Regulation
LNREG
V
DD =
±10 V
0.04
%/V max
Reference Output Current
IREFOUT
V
REFOUT < 40 mV
5
mA min
Logic Inputs High
VINH
2.4
V min
Logic Inputs Low
VINL
0.8
V max
Logic Input Current
IIN
VIN = 0 V or VDD
±1
A max
Positive Supply Current
IDD
VIN = VINL or VINH
14
mA max
Negative Supply Current
ISS
VIN = VINL or VINH’ VSS = –5 V
10
mA max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
WAFER TEST LIMITS at V
DD = +15 V
5%; VSS = AGND = DGND = 0 V; unless otherwise specified. TA = +25 C. All specifications
apply for DACs A, B, C, and D.
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