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參數(shù)資料
| 型號(hào)： | DAC8248FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 12-BIT DAC, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | DAC8248FP |
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DAC8248
–9–
REV. B
Figure 2. N-Channel Current Steering Switch
T he binary-weighted currents are switched between I
OUT
and
AGND by the transistor switches. Selection between I
OUT
and
AGND is determined by the digital input code. It is important
to keep the voltage difference between I
OUT
and AGND termi-
nals as close to zero as practical to preserve data sheet limits. It
is easily accomplished by connecting the DAC’s AGND to the
noninverting input of an operational amplifier and I
OUT
to the
inverting input. T he amplifier’s feedback resistor can be elimi-
nated by connecting the op amp’s output directly to the DAC’s
R
FB
terminal (by using the DAC’s internal feedback resistor,
R
FB
). T he amplifier also provides the current-to-voltage conver-
sion for the DAC’s output current.
T he output voltage is dependent on the DAC’s digital input
code and V
REF
, and is given by:
V
OUT
= V
REF
×
D/
4096
where
D
is the digital input code integer number that is between
0 and 4095.
T he DAC’s input resistance, R
REF
, is always equal to a constant
value, R. T his means that V
REF
can be driven by a reference
voltage or current, ac or dc (positive or negative). It is recom-
mended that a low temperature-coefficient external R
FB
resistor
be used if a current source is employed.
T he DAC’s output capacitance (C
OUT
) is code dependent and
varies from 90 pF (all digital inputs low) to 120 pF (all digital
inputs high).
T o ensure accuracy over the full operating temperature range,
permanently turned “ON” MOS transistor switches were in-
cluded in series with the feedback resistor (R
FB
) and the R-2R
ladder’s terminating resistor (see Figure 1). T he gates of these
NMOS transistors are internally connected to V
DD
and will be
turned “OFF” (open) if V
DD
is not applied. If an op amp is us-
ing the DAC’s R
FB
resistor to close its feedback loop, then V
DD
must be applied before or at the same time as the op amp’s sup-
ply; this will prevent the op amp’s output from becoming “open
circuited” and swinging to either rail. In addition, some applica-
tions require the DAC’s ladder resistance to fall within a certain
range and are measured at incoming inspection; V
DD
must be
applied before these measurements can be made.
DIGIT AL SE CT ION
T he DAC8248’s digital inputs are T T L compatible at V
DD
= +5 V
and CMOS compatible at V
DD
= +15 V. T hey were designed to
convert T T L and CMOS input logic levels into voltage levels that
will drive the internal circuitry. T he DAC8248 can use +5 V
CMOS logic levels with V
DD
= +12 V; however, supply current
will increase to approximately 5 mA–6 mA.
Figure 3 shows the DAC’s digital input structure for one bit.
T his circuitry drives the DAC registers. Digital controls,
φ
and
φ
, shown are generated from the DAC’s input control logic
circuitry.
Figure 3. Digital Input Structure For One Bit
T he digital inputs are electrostatic-discharge (ESD) protected
with two internal distributed diodes as shown in Figure 3; they
are connected between V
DD
and DGND. Each input has a typi-
cal input current of less than 1 nA.
T he digital inputs are CMOS inverters and draw supply current
when operating in their linear region. Using a +5 V supply, the
linear region is between +1.2 V to +2.8 V with current peaking
at +1.8 V. Using a +15 V supply, the linear region is from
+1.2 V to +12 V (current peaking at +3.9 V). It is recom-
mended that the digital inputs be operated as close to the power
supply voltage and DGND as is practically possible; this will
keep supply currents to a minimum. T he DAC8248 may be
operated with any supply voltage between the range of +5 V to
+15 V and still perform to data sheet limits.
T he DAC8248’s 8-bit wide data port loads a 12-bit word in two
bytes: 8-bits then 4-bits (or 4-bits first then 8-bits, at users dis-
cretion) in a right justified data format. T his data is loaded into
the input registers with the
LSB
/MSB and
WR
control pins.
Data transfer from the input registers to the DAC registers can
be automatic. It can occur upon loading of the second data byte
into the input register, or can occur at a later time through a
strobed transfer using the
LDAC
control pin.
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參數(shù)描述 |
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| DAC8248FPZ | 功能描述:IC DAC 12BIT DUAL BUFFERD 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| DAC8248FPZ | 制造商:Analog Devices 功能描述:12BIT DAC CMOS DUAL 8248 DIP24 |
| DAC8248FS | 功能描述:IC DAC 12BIT DUAL W/BUFF 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| DAC8248FS-REEL | 功能描述:IC DAC 12BIT DUAL W/BUFF 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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