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參數(shù)資料
| 型號(hào)： | DAC8248FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 12-BIT DAC, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 350K |
| 代理商： | DAC8248FP |
DAC8248
–11–
REV. B
AUT OMAT IC DAT A T RANSFE R MODE
Data may be transferred automatically from the input register to
the DAC register. T he first cycle loads the first data byte into
the input register; the second cycle loads the second data byte
and simultaneously transfers the full 12-bit data word to the
DAC register. It takes four cycles to load and transfer two com-
plete digital words for both DAC’s, see Figure 4 (Four Cycle
Update T iming Diagram) and the Mode Selection T able.
ST ROBE D DAT A T RANSFE R MODE
Strobed data transfer allows the full 12-bit digital word to be
loaded into the input registers and transferred to the DAC regis-
ters at a later time. T his transfer mode requires five cycles: four
to load two new data words into both DACs, and the fifth to
transfer all data into the DAC registers. See Figure 5 (Five Cycle
Update T iming Diagram) and the Mode Selection T able.
Strobed data transfer separating data loading and transfer op-
erations serves two functions: the DAC output updating may be
more precisely controlled, and multiple DACs in a multiple
DAC system can be updated simultaneously.
RE SE T
T he DAC8248 comes with a
RESET
pin that is useful in system
calibration cycles and/or during system power-up. All registers
are reset to zero when
RESET
is low, and latched at zero on the
rising edge of the
RESET
signal when
WRITE
is high.
INT E RFACE CONT ROL LOGIC
T he DAC8248’s control logic is shown in Figure 6. T his cir-
cuitry interfaces with the system bus and controls the DAC
functions.
Figure 6. Input Control Logic
MODE SE LE CT ION T ABLE
DIGIT AL INPUT S
RE GIST E R ST AT US
DAC A
DAC
MSB
Register
DAC B
Input Register
LSB
Input Register
LSB
DAC
Register
DAC A
/B
WR
LSB
/MSB
RESET
LDAC
MSB
L
L
L
L
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
H
H
X
H
L
L
H
H
L
L
H
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
g
H
L
H
L
H
L
H
L
H
L
X
X
WR
WR
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
ALL REGIST ERS ARE RESET T O ZEROS
ZEROS ARE LAT CHED IN ALL REGIST ERS
LAT
LAT
WR
WR
LAT
LAT
LAT
LAT
LAT
LAT
LAT
WR
LAT
WR
LAT
WR
LAT
WR
LAT
WR
LAT
LAT
LAT
LAT
WR
WR
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
WR
WR
LAT
LAT
LAT
WR
LAT
WR
LAT
WR
LAT
WR
LAT
WR
L = Low, H = High, X = Don’t Care, WR = Registers Being Loaded, LAT = Registers Latched.
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