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參數(shù)資料
| 型號： | DAC8222FSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL W/BUFF 24-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 1µs |
| 位數(shù)： | 12 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1M |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
DAC8222
–9–
REV. C
Table I. Mode Selection
Digital Inputs
Register Status
DAC A
DAC B
DAC
A/B
WR
LDAC
Input Register
DAC Register
Input Register
DAC Register
L
WRITE
LATCHED
WRITE
H
L
LATCHED
WRITE
L
H
WRITE
LATCHED
H
L
H
LATCHED
WRITE
LATCHED
X
H
L
LATCHED
WRITE
LATCHED
WRITE
X
H
LATCHED
L = Low, H = High, X = Don’t Care
WRITE TIMING CYCLES
Two timing diagrams are shown and are at the user’s discretion
which to use.
The TWO-CYCLE UPDATE, as the name implies, allows both
DAC registers to be loaded and the outputs updated in two
cycles. Data is first loaded into one DAC’s input register on the
first write cycle, and then new data loaded into the other DAC’s
input register while simultaneously updating both DAC outputs
on the second cycle.
The THREE-CYCLE UPDATE allows
DAC A and DAC B
registers to be loaded and analog output to be updated at a later
time. The first two cycles load both DACs as above, and the
third cycle updates the outputs.
The
LDAC and DAC A/DAC B control pins can be tied to-
gether and controlled with a single strobe. When using the DAC
in this configuration, DAC B must be loaded first.
INTERFACE CONTROL LOGIC
DAC A/DAC B (Pin 18)–DAC Selection. Active low for
DAC A and active high for DAC B.
WR (Pin 20)–WRITE. Active Low. Used to write data into
either DAC A or DAC B input registers, or active high latches
data into the input registers.
LDAC (Pin 19)–LOAD DAC. Active Low. Used to simulta-
neously transfer data from
DAC A and DAC B input registers
to both DAC outputs. The DAC becomes transparent (activity
on the digital inputs appear at the analog output) when both
WR and LDAC are low. Data is latched into the output regis-
ters on the rising edge of
LDAC.
Three-Cycle Update
Figure 23. Write Cycle Timing Diagram
Two-Cycle Update
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC8222FSZ-REEL | 功能描述:IC DAC 12BIT DUAL CMOS 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| DAC8222FW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DAC8222GBC | 制造商:Analog Devices 功能描述: |
| DAC8222GP | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 24-Pin PDIP Tube 制造商:Rochester Electronics LLC 功能描述:DUAL 12-BIT CMOS DAC WITH - Bulk |
| DAC8222GPZ | 功能描述:IC DAC 12BIT DUAL W/BUFF 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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