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參數(shù)資料
| 型號(hào)： | DAC8143FP |
| 廠商： | PRECISION MONOLITHICS INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Serial Daisy-Chain CMOS D/A Converter |
| 中文描述： | 12-BIT DAC, PDIP16 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | DAC8143FP |
DAC8143
–8–
REV. C
Where R
O
is a function of the digital code, and:
R
O
= 10 k
for more than four bits of Logic 1,
R
O
= 30 k
for any single bit of Logic 1.
Therefore, the offset gain varies as follows:
at code 0011 1111 1111,
V
ERROR
1
=
V
OS
1
+
10
k
10
k
= 2
V
OS
at code 0100 0000 0000,
V
ERROR
2
=
V
OS
1
+
10
k
30
k
= 4/3
V
OS
The error difference is 2/3 V
OS
.
Since one LSB has a weight (for V
REF
= +10 V) of 2.4 mV for
the DAC8143, it is clearly important that V
OS
be minimized,
using either the amplifier’s pulling pins, an external pulling
network, or by selection of an amplifier with inherently low V
OS
.
Amplifiers with sufficiently low V
OS
include OP77, OP97, OP07,
OP27, and OP42.
INTERFACE LOGIC OPERATION
The microprocessor interface of the DAC8143 has been design-
ed with multiple STROBE and LOAD inputs to maximize inter-
facing options. Control signals decoding may be done on chip or
with the use of external decoding circuitry (see Figure 21).
Serial data is clocked into the input register and buffered output
stage with STB
1
, STB
2
, or STB
4
. The strobe inputs are active
on the rising edge.
STB
3
may be used with a falling edge clock
data.
WORD N
WORD N –1
WORD N –2
WORD N –1
WORD N
BIT 11
BIT 2
BIT 12
LSB
BIT 1
MSB
BIT 12
LSB
BIT 2
BIT 1
MSB
SRI
BIT 2
BIT 1
MSB
BIT 1
MSB
BIT 2
BIT 12
LSB
BIT 1
LSB
t
DS1
,
t
DS2
,
t
DS3
,
t
DS4
SRO
t
DH1
,
t
DH2
,
t
DH3
,
t
DH4
t
PD
t
STB1
t
STB2
t
STB3
t
STB4
t
STB1
t
STB2
t
STB3
t
STB4
*
STROBE
(STB
1
, STB
2
, STB
4
)
1
2
12
1
2
t
LD1
t
LD2
t
SR1
12
11
t
ASB
LD
1
AND LD
2
LOAD NEW 12-BIT WORD INTO
INPUT REGISTER AND SHIFT
OUT PREVIOUS WORD
LOAD INPUT REGISTER'S
DATA INTO DAC REGISTER
NOTES:
*
STROBE WAVEFORM IS INVERTED IF
STB
3
IS USED TO STROBE SERIAL DATA
BITS INTO INPUT REGISTER.
**
DATA IS STROBED INTO AND OUT OF
THE INPUT SHIFT REGISTER MSB FIRST.
Figure 15. Timing Diagram
Serial data output (SRO) follows the serial data input (SRI) by
12 clocked bits.
Holding any STROBE input at its selected state (i.e., STB
1
,
STB
2
or STB
4
at logic HIGH or STB
3
at logic LOW) will act to
prevent any further data input.
When a new data word has been entered into the input register,
it is transferred to the DAC register by asserting both LOAD
inputs.
The
CLR
input allows asynchronous resetting of the DAC regis-
ter to 0000 0000 0000. This reset does not affect data held in
the input registers. While in unipolar mode, a CLEAR will
result in the analog output going to 0 V. In bipolar mode, the
output will go to –V
REF
.
INTERFACE INPUT DESCRIPTION
STB
1
(Pin 4), STB
2
(Pin 8), STB
4
(Pin 11)—Input Register
and Buffered Output Strobe. Inputs Active on Rising
Edge.
Selected to load serial data into input register and buff-
ered output stage. See Table I for details.
STB
3
(Pin 10)—Input Register and Buffered Output
Strobe Input. Active on Falling Edge.
Selected to load serial
data into input register and buffered output stage. See Table I
for details.
LD
1
(Pin 5),
LD
2
(Pin 9)—Load DAC Register Inputs.
Active Low.
Selected together to load contents of input register
into DAC register.
CLR
(Pin 13)—Clear Input. Active Low. Asynchronous.
When LOW, 12-bit DAC register is forced to a zero code (0000
0000 0000) regardless of other interface inputs.
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