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參數(shù)資料
| 型號： | DAC811SH |
| 英文描述： | Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 微處理器兼容的12位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/9頁 |
| 文件大小： | 96K |
| 代理商： | DAC811SH |
9
DAC811
INTERFACING MULTIPLE DAC811s
IN 8-BIT SYSTEMS
Many applications, such as automatic test systems, require
that the outputs of several D/A converters be updated simul-
taneously. The interface shown in Figure 12 uses a 74LS138
decoder to decode a set of eight adjacent addresses, to load
the input latches of four DAC811s. The example shows a
right-justified data format.
A ninth address using A
3
causes all DAC811s to be updated
simultaneously. If a particular DAC811 is always loaded
last—for instance, D/A #4—A
3
is not needed, thus saving
ADDRESS BUS
A2
A3
A1
A0
OPERATION
0
0
0
0
Load 8 LSB – D/A #1
0
0
0
1
Load 4 MSB – D/A #1
0
0
1
0
Load 8 MSB – D/A #2
0
0
1
1
Load 4 MSB – D/A #2
0
1
0
0
Load 8 MSB – D/A #3
0
1
0
1
Load 4 MSB – D/A #3
0
1
1
0
Load 8 MSB – D/A #4
0
1
1
1
Load 4 MSB – D/A #4
1
X
X
X
Load D/A Latch—All D/A
FIGURE 12. Interfacing Multiple DAC811s to an 8-Bit Bus.
eight address spaces for other uses. Incorporate A
3
into the
base address decoder, remove the inverter, connect the
common LDAC line to N
C
of D/A #4, and connect D1 of the
74LS138 to +5V.
12- AND 16-BIT MICROCOMPUTER INTERFACE
For this application, the input latch enable lines, N
A
, N
B
and
N
C,
are tied low, causing the latches to be transparent. The
D/A latch, and therefore DAC811, is selected by the address
decoder and strobed by WR.
Base
Address
Decoder
WR
A
A
15
4
A
A
A
2
1
0
M
A
3
74LS138
C
B
A
G
G
G
2A
2B
1
WR
LDAC
N
N
N
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
3
2
1
4
6
5
CS
DAC811
(4)
C
B
WR
LDAC
N
N
N
A
DAC811
(1)
C
B
WR
LDAC
N
N
N
A
DAC811
(2)
C
B
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