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參數資料
| 型號： | DAC811SH |
| 英文描述： | Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 微處理器兼容的12位數字到模擬轉換器 |
| 文件頁數： | 8/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | DAC811SH |
DAC811
8
FIGURE 10. Right-Justified Data Bus Interface.
FIGURE 11. Left-Justified Data Bus Interface.
8-BIT INTERFACE
The control logic of DAC811 permits interfacing to right-
justified data formats, as illustrated in Figure 9. When a
12-bit D/A converter is loaded from an 8-bit bus, two bytes
of data are required. Figures 10 and 11 show an addressing
scheme for right-justified and left-justified data respectively.
The base address is decoded from the high-order address
bits. A
0
and A
1
address the appropriate latches. Note that
adjacent addresses are used. For the right-justified case,
X10
16
loads the 8LSBs, and X01
16
loads the 4MSBs and
simultaneously transfers input latch data to the D/A latch.
Addresses X00
16
and X11
16
are not used.
Left-justified data is handled in a similar manner, shown in
Figure 11. The DAC811 still occupies two adjacent loca-
tions in the microcomputer's memory map.
FIGURE 8. Addressing and Control for 4-Bit Microcom-
puter Interface.
FIGURE 9. 12-Bit Data Format for 8-Bit Systems.
D0
D4
D8
D1
D5
D9
D2
D6
D10
D3
D7
D11
16
14
10
17
13
9
18
12
8
19
11
7
DB0
DB1
DB2
DB3
WR
A
A
A
1
0
M
D
Base
Address
Decoder
A
N
2
2
3
4
5
6
WR
LDAC
N
N
N
1/2
74LS139
A
B
C
7
6
5
4
1
3
2
CS
(Chip
Select)
A
A
1
0
EN
Y
Y
Y
Y
3
2
1
0
X
X
X
X
D11 D10
D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
a. Right-Justified
D11 D10
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
b. Left-Justified
X
X
X
X
D0
D8
D1
D9
D2
D10
D3
D11
D4
D5
D6
D7
16
10
17
9
18
8
19
7
14
13
12
11
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
WR
A
A
1
0
M
D
Base
Address
Decoder
A
A
15
2
2
3
4
5
6
WR
LDAC
N
N
N
A
B
C
CS
D4
D5
D6
D7
D8
D0
D9
D1
D10
D2
D11
D3
14
13
12
11
10
16
9
17
8
18
7
19
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
WR
A
A
1
0
M
D
Base
Address
Decoder
A
A
15
2
2
3
4
5
6
WR
LDAC
N
N
N
A
B
C
CS
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