參數(shù)資料
型號(hào): DAC7811IDRCR
廠商: Texas Instruments, Inc.
英文描述: 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter
中文描述: 12位,串行輸入,乘法數(shù)字到模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 12/18頁(yè)
文件大?。?/td> 698K
代理商: DAC7811IDRCR
www.ti.com
P
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 29), the DAC7811 current output (I
OUT
) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design. For each code change, there is a step function. If the gain bandwidth product (GBP) of the op amp
is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible. Therefore,
for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in
Figure 29.
I
OUT1
V
OUT
R
FB
C
1
GND
V
DD
V
DD
U1
U2
V
REF
V
REF
I
OUT2
Positive Voltage Output Circuit
As Figure 30 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7811. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, V
OUT
and GND of the reference are level-shifted to a virtual ground
and a –2.5 V input to the DAC7811 with an op amp.
DAC7811
SBAS337–APRIL 2005
Table 3. Serial Input Register Data Format, Data Loaded MSB First
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION IMPLEMENTED
No operation (power-on default)
Load and update
Initiate readback
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Daisy-chain disable
Clock data to shift register on rising edge
Clear DAC output to 0
Clear DAC output to midscale
Reserved
Reserved
Reserved
Figure 29. Gain Peaking Prevention Circuit with Compensation Capacitor
12
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