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參數(shù)資料
| 型號： | DAC7811IDRCR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter |
| 中文描述： | 12位，串行輸入，乘法數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 698K |
| 代理商： | DAC7811IDRCR |
www.ti.com
P
OPA277
DAC7811
I
OUT1
V
OUT
15V
V+
V
15V
R
FB
GND
V
DD
V
DD
V
REF
I
OUT2
Serial Interface
Input Shift Register
DAC7811
SBAS337–APRIL 2005
Theory of Operation (continued)
For best linearity performance of the DAC7811, an op amp (OPA277) is recommended (see Figure 26). This
circuit allows V
REF
swinging from –10 V to +10 V.
Figure 26. Voltage Output Configuration
Table 2. Control Logic Truth Table
(1)
CLK
X
↑
+
X
SYNC
H
L
↑
+
SERIAL SHIFT REGISTER
DAC REGISTER
No effect
Shift register data advanced one bit
In daisy-chain mode the function as determined by
C3-C0 is executed.
Latched
Latched
In daisy-chain mode the contents may chage
as determined by C3-C0.
(1)
↑
+
Positive logic transition;
X
= Do not care.
The DAC7811 has a three-wire serial interface (SYNC, SCLK, and SDIN), which is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most Digital Signal Processor (DSP) devices. See the Serial
Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by
bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50MHz, making the DAC7811 compatible with high-speed
DSPs. The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power
dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK
input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low,
but before the first active clock edge, it will be ignored. If the SDO pin is being used then SYNC must remain low
until after the inactive clock edge that follows the 16th active clock edge.
The input shift register is 16 bits wide, as shown in Figure 27. The four MSBs are the control bits C3 – C0; these
bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the 16th active
clock edge in stand-alone mode. The remaining 12 bits are the data bits. On a load and update command
(C3–C0 = 0001) these 12 data bits will be transferred to the DAC register; otherwise, they have no effect.
4 CONTROL BITS
C2
12 DATA BITS
DB6
C3
C1
C0
DB11
DB10
DB9
DB8
DB7
DB5
DB4
DB3
DB2
DB1
DB0
MSB
DB15
LSB
Figure 27. Contents of the 16-Bit Input Shift Register
10
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7811IDRCT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit, Serial Input, Multiplying Digital-to-Analog Converter |
| DAC7821 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit, Parallel Input, Multiplying Digital-to-Analog Converter |
| DAC7821IPW | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Parallel Inp Multiplying DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7821IPW | 制造商:Texas Instruments 功能描述:D/A CONVERTER (D-A) IC |
| DAC7821IPWG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-bit Parallel Inp Multiplying DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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