參數(shù)資料
型號(hào): DAC7742
英文描述: 16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface
中文描述: 16位,單通道數(shù)字到模擬轉(zhuǎn)換器,具有內(nèi)部參考和并行接口
文件頁(yè)數(shù): 14/19頁(yè)
文件大?。?/td> 376K
代理商: DAC7742
DAC7742
SBAS256
14
www.ti.com
DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a LOW signal
on RST. Once RST is LOW, the DAC output will begin settling
to the mid-scale or min-scale code depending on the state of
the RSTSEL input. A HIGH value on RSTSEL will cause V
OUT
to reset to the mid-scale code (7FFF
H
) and a LOW value will
reset V
OUT
to min-scale (FFFF
H
). A change in the state of the
RSTSEL input while RST is LOW will cause a corresponding
change in the reset command selected internally and conse-
quently change the output value of V
OUT
of the DAC. Note that
a valid reset signal also resets the input register of the DAC to
the value specified by the state of RSTSEL.
GAIN AND OFFSET CALIBRATION
The architecture of the DAC7742 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7742
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 5 and 6 illustrate the
relationship of offset and gain adjustments for the DAC7742
in a unipolar configuration and in a bipolar configuration,
respectively.
When calibrating the DAC
s output, offset should be adjusted
first to avoid 1st-order interaction of adjustments. In unipolar
mode, the DAC7742
s offset is adjusted from code FFFF
H
and for either bipolar mode, offset adjustments are made at
code 7FFF
H
. Gain adjustment can then be made at code
0000
H
for each configuration, where the output of the DAC
should be at +10V for the 0V to +10V
1LSB or
±
10V output
range and +5V
1LSB for the
±
5V output range. Figure 7
shows the generalized external offset and gain adjustment
circuitry using potentiometers.
Digital Input
H
Input =
0000
H
Input =
FFFF
Gain Adjust
Rotates
the Line
1LSB
+ Full-Scale
F
A
(+V
REF
)
Zero Scale
(AGND)
Offset Adjust Translates the Line
Digital Input
Input =
FFFF
H
Gain
Adjust
Rotates
the Line
1LSB
F
R
+ Full-
Scale
Full-Scale
(
V
REF
OR
V
REF
/2)
Offset
Adjust
Translates
the Line
H
Input =
0000
Input = 7FFF
H
A
(+V
REF
or +V
REF
/2)
FIGURE 5. Relationship of Offset and Gain Adjustments for
V
OUT
= 0V to +10V Output Configuration.
FIGURE 6. Relationship of Offset and Gain Adjustments for
V
OUT
=
10V to +10V Output Configuration. (Same
Theory Applies for V
OUT
=
5V to +5V.)
FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.
N
V
S
V
C
V
R
R
O
A
A
R
R
S
V
O
1
2
3
4
5
6
7
8
9
1
1
15
16
17
18
Optional Gain
Adjust
(Other Connections Omitted
for Clarity)
REF
OUT
REFADJ
REF
IN
NC
Optional Offset
Adjust
R
POT1
R
S
V
OADJ
+
I
SJ
R
1
R
POT2
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