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參數(shù)資料
| 型號(hào)： | DAC707KP |
| 英文描述： | Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS |
| 中文描述： | 微處理器兼容的16位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | DAC707KP |
DAC707/708/709
8
VOLTAGE OUTPUT MODELS
Analog Output
Analog Output
Unipolar, 0 to +10V
(1)
Bipolar,
±
10V
Bipolar,
±
5V
16-Bit
15-Bit
14-Bit
Units
16-Bit
15-Bit
14-Bit
16-Bit
15-Bit
14-Bit
Units
One LSB
FFFF
H
0000
H
153
305
610
μ
V
V
V
One LSB
7FFFH
8000H
305
610
1224
+9.99878
–10.0000
153
305
610
μ
V
V
V
+9.99985
0
+9.99969
0
+9.99939
0
+9.99960
–10.0000
+9.99939
–10.0000
+4.99980
–5.0000
+4.99970
–5.0000
+4.99939
–5.0000
CURRENT OUTPUT MODELS
Analog Output
Analog Output
Bipolar,
±
1mA
Unipolar, 0 to –2mA
(1)
16-Bit
15-Bit
14-Bit
Units
16-Bit
15-Bit
14-Bit
Units
One LSB
FFFF
H
0000
H
0.031
–1.99997
0
0.061
–1.99994
0
0.122
–1.99988
0
μ
A
mA
mA
One LSB
7FFF
H
8000
H
0.031
–0.99997
+1.00000
0.061
–0.99994
+1.00000
0.122
–0.99988
+1.00000
μ
A
mA
mA
Digital
Input
Code
Digital
Input
Code
Digital
Input
Code
Digital
Input
Code
TABLE II. Digital Input and Analog Output Voltage/Current Relationships.
NOTE: (1) MSB assumed to be inverted externally.
INTERFACE LOGIC AND TIMING
DAC708/709
The signals CHIP SELECT (CS), WRITE (WR), register
enables (A
, A
, and A
) and CLEAR (CLR), provide the
control functions for the microprocessor interface. They are
all active in the “l(fā)ow” or logic “0” state. CS must be low to
access any of the registers. A
and A
steer the input 8-bit
data byte to the low- or high-byte input latch respectively. A
2
gates the contents of the two input latches through to the D/A
latch in parallel. The contents are then applied to the input of
the D/A converter. When WR goes low, data is strobed into
the latch or latches which have been enabled.
The serial input mode is activated when both A
and A
are
logic “0” simultaneously. The D0 (D8)/SI input data line
accepts the serial data MSB first. Each bit is clocked in by
a WR pulse. Data is strobed through to the D/A latch by A
2
going to logic “0” the same as in the parallel input mode.
Each of the latches can be made “transparent” by maintain-
ing its enable signal at logic “0”. However, as stated above,
when both A
and A
are logic “0” at the same time, the
serial mode is selected.
The CLR line resets both input latches to all zeros and sets
the D/A latch to 0000
. This is the binary code that gives a
In the unipolar mode, activating CLR will cause the output
to go to one-half of full scale.
The maximum clock rate of the latches is 10MHz. The
minimum time between write (WR) pulses for successive
enables is 20ns. In the serial input mode (DAC708 and
DAC709), the maximum rate at which data can be clocked
into the input shift register is 10MHz.
The timing of the control signals is given in Figure 6.
DAC707
The DAC707 interface timing is the same as that described
above except instead of two 8-bit separately-enabled input
latches, it has a single 16-bit input latch enabled by A
0
. The
TIMING DIAGRAM
D0-D15, SI
WR
CS
t
CW
t
DW
A
0
, A
1
, A
2
t
AW
t
DH
t
WP
LOGIC TIMING - Parallel or Serial Data Input Over Temperature
ns, min
80
80
80
80
ns, max
T
DW
T
CW
T
AW
T
WP
T
DH
Data valid to end of WR
CS valid to end of WR
A
, A
, A
valid to end of WR
Write pulse width
Data hold after end of WR
0
FIGURE 6. Logic Timing Diagram.
D/A latch is enabled by A
. Also, there is no serial-input
mode and no CHIP SELECT (CS) line.
INSTALLATION
CONSIDERATIONS
Due to the extremely-high accuracy of the D/A converter,
system design problems such as grounding and contact
resistance become very important. For a 16-bit converter
with a +10V full-scale range, 1LSB is 153
μ
V. With a load
current of 5mA, series wiring and connector resistance of
only 30m
will cause the output to be in error by 1LSB. To
understand what this means in terms of a system layout, the
resistance of typical 1 ounce copper-clad printed circuit
board material is approximately 1/2m
per square. In the
example above, a 10 milliinch-wide conductor 60 milliinches
long would cause a 1LSB error.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC708 | Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS |
| DAC709BH | RES 1.10 OHM 1/4W 1% 0805 SMD |
| DAC709SH | Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS |
| DAC708 | Microprocessor-Compatible 16-Bit Dightal-To-Analog Converter(微處理器兼容的16位D/A轉(zhuǎn)換器) |
| DAC712 | 16-BIT DIGITAL-TO-ANALOG CONVERTER With 16-Bit Bus Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC707KP-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DAC707KP-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DAC707KP-5 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS |
| DAC707KP-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:FOR EAGLE TEST ONLY - Rail/Tube |
| DAC707KP-7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
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