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參數(shù)資料
| 型號： | DAC600 |
| 英文描述： | 12-Bit 256MHz Monolithic DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 12位256MHz單片數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | DAC600 |
DAC600
11
FIGURE 5. Timing Diagram.
Clock 1
t
PWL
t
PWH
Data 1
V
OUT
1
t
P
t
PLSB
t
PMSB
CLK
Data
V
OUT
t
P
t
SU
t
H
t
PWL
t
PWH
t
PMSB
t
PLSB
Propagation delay. 50% of CLK to 50% of V
OUT
.
Setup time DATA must remain stable before CLK.
Hold time DATA must remain stable after CLK.
CLK pulse width low (50% to 50%).
CLK pulse width high (50% to 50%).
Propagation delay, MSBs, transparent mode only.
Propagation delay, LSBs, transparent mode only.
SYMBOL
DESCRIPTION
MIN
2
1.0
1.7
2.1
1.5
TYP
MAX
ns
ps
ns
ns
ns
ns
ns
UNITS
t
H
t
SU
1.5
1.9
1.95
1.95
Clock 0
Clock 2
Data 2
Data 0
analog ground plane. For speeds of up to 256MHz, series
termination with 47
resistors will be adequate (Figure 6).
This termination technique will greatly lessen the issue of
termination currents coupling into the analog ground plane.
This is shown in the typical DAC600 connection diagram
(Figure 7.)
FIGURE 6. Series Bit Termination.
DAC600
47
ECL Drive Gates
Bit
Input
–5.2V
Recommended
Pull Down Resistor
LAYOUT AND POWER SUPPLIES
A multilayer PC board with a solid ground and power planes
is recommended. All of the ground pins (both analog and
digital) should be connected directly to the analog ground
plane at the DAC600.
Wide busses for the power paths are recommended as good
general practice. External bypassing is recommended. A
10
μ
F ceramic capacitor in parallel with a 0.01
μ
F chip
capacitor will be sufficient in most applications.
ALTCOMPB and ALTCOMPC should be bypassed with
0.1
μ
F capacitors connected to V
EEA
. When not used in the
multiplying mode LBIAS should be bypassed with a 0.4
μ
F
capacitor connected to V
EEA
. The heat spreader (pins 26 and
44) should be bypassed with a 0.1
μ
F capacitor.
MAXIMIZING PERFORMANCE
In addition to optimizing the layout and ground of the
DAC600, there are other important issues to consider when
optimizing the performance of this DAC in various AC
applications.
The DAC600 includes an internal 50
output impedance to
simplify output interfacing to a 50
load. Because some
loads may be a complex impedance, care must be taken to
match the output impedance with the load. Mismatching of
impedances can cause reflections which will affect the
measured AC performance parameters such as settling time,
harmonic distortion, rise/fall times, etc. Often complex im-
pedances can be matched by placing a variable 3 to 10pF
capacitor at the output of the DAC to ground. Also, probing
the output of the DAC can present a complex impedance.
The typical performance curves of Spurious Free Dynamic
Range vs various combinations of clock rate and/or input
frequency should give a general idea of the spectral perfor-
mance of the DAC under system specific clock and output
frequencies. For variable frequency DDS and ARB applica-
tions, having a programmable frequency bandpass (smart)
filter at the output of the DAC can greatly improve system
相關(guān)PDF資料 |
PDF描述 |
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| DAC600 | 12-Bit 256MHz Monolithic Dightal-To-Analog Converter(12位 256MHz單片D/A轉(zhuǎn)換器) |
| DAC650 | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| DAC650JL | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| DAC650KL | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| DAC650 | 12-Bit 500MHz Dightal-To-Analog Converter(12位 500M赫茲單片D/A轉(zhuǎn)換器) |
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