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參數(shù)資料
| 型號(hào)： | DAC600 |
| 英文描述： | 12-Bit 256MHz Monolithic DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 12位256MHz單片數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | DAC600 |
DAC600
10
There is also a complementary V
OUT NOT
output that allows
for a differential output signal. The full scale complementary
outputs (V
OUT
and V
OUT NOT
) can be simply modeled as
–20mA in parallel with 50
. This gives an output swing of
0.5Vp-p with an external 50
load.
REFERENCE/GAIN ADJUSTMENT
The V
REF
pin should be supplied by a +1.0V reference that
is capable of supplying a nominal current of 1.25mA. An
alternative would be the use of a 1.25mA current source. A
low drift reference will minimize gain drift. A recommended
reference circuit is given in Figure 2 as shown in the Typical
Performance Curves, lowering the reference voltage to +0.8V
will typically improve the Spurious Free Dynamic Range by
a few dB.
FIGURE 2. A Low Drift External Reference Circuit.
A low-cost alternative reference circuit is shown in Figure
3. This circuit uses the Burr-Brown REF1004-2.5
micropower voltage reference. Gain drift is dependent upon
the temperature coefficient of the 1.2k
resistor. A TC of
< 10ppm/
°
C is recommended.
The DAC600 can also accept a wideband multiplying
reference input. The full power bandwidth of this reference
is approximately 30MHz. Care must be taken not to exceed
the minimum and maximum input reference voltage levels
which are 100mV and +1.25V respectively (refer to the
absolute maximum ratings section). In the multiplying
reference mode, the 0.4
μ
F bypass capacitor on LBIAS and
the 0.1
μ
F on pin 35 need to be removed. A 47pF capacitor
to ground needs to be connected to pin 35 (Figure 4.)
REF1004-2.5
1.8k
1.2k
+1V
REFOUT
+5V
FIGURE 3. Low Cost External Reference Circuit.
FIGURE 4. Connections for a Multiplying Reference Input.
DAC600
39
38
35
47pF
(AC Ref Input)
50
(Open)
LBIAS
V
REF2
V
REF
V
REF
TIMING
The DAC600 has an internal latch that is triggered on the
rising edge of the clock when the BYPASS pin is set LOW.
This master-slave mode of operation will assure that the 12
bits will arrive at the current sources with a minimum of data
skew. Therefore, this mode is recommended for the vast
majority of applications. Observing the minimum set-up and
hold time recommendations will ensure proper data latching,
refer to Figure 5 for complete timing specifications.
When BYPASS is set HIGH, the DAC600 will operate in
the transparent mode. In this mode, both the master and
slave registers are transparent and changes in input data
ripple directly to the output. Since the four MSBs have a
decoder delay, these bits arrive at the output approximately
600 picoseconds later than the lower 8 LSBs. Because this
optimum AC performance.
The DAC600 has a differential ECL clock input. This clock
input can also be driven by a single ended clock if desired
by trying the CLKNOT input to an external voltage of
–1.3V. Using a differential clock provides much improved
digital feedthrough immunity, however.
DRIVING THE DAC600
The DAC600 inputs will most likely be driven by high speed
ECL gate outputs. These outputs should be terminated using
standard high speed transmission line techniques. Consult an
ECL handbook for proper methods of termination.
Termination resistors should not be connected to the analog
ground plane close to the DAC600. The fast changing digital
bit currents will cause noise in the analog ground plane
under this layout scheme. These fast changing digital cur-
rents should be steered away from the sensitive DAC600
OPA602
0.1μF
+5V
0.1μF
–5V
–V
S
+V
S
Out
+1V
REF OUT
0.1μF
100μA
REF200
8
6
+5V
100
(1)
10k
(1)
0.01μF
NOTE: (1) 50 to 100 ppm/°C resistors.
1
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| DAC600 | 12-Bit 256MHz Monolithic Dightal-To-Analog Converter(12位 256MHz單片D/A轉(zhuǎn)換器) |
| DAC650 | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| DAC650JL | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| DAC650KL | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| DAC650 | 12-Bit 500MHz Dightal-To-Analog Converter(12位 500M赫茲單片D/A轉(zhuǎn)換器) |
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