
DAC4813
3
ABSOLUTE MAXIMUM RATINGS
+V
CC
to ACOM ............................................................................ 0 to +18V
–V
CC
to ACOM ............................................................................ 0 to –18V
+V
to –V
...............................................................................0 to +36V
ACOM to DCOM ..................................................................................
±
4V
Digital Inputs to DCOM ...........................................................–1V to +V
CC
External Voltage applied to BPO Resistor .........................................
±
18V
V
REF OUT
.............................................................. Indefinite short to ACOM
V
±
18V
Lead Temperature, soldering 10s .................................................. +300
o
C
Max Junction Temperature .............................................................. 165
o
C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE
DRAWING
NUMBER
(1)
TEMPERATURE
RANGE
PRODUCT
PACKAGE
DAC4813AP
DAC4813JP
28-Pin Plastic DBL Wide DIP
28-Pin Plastic DBL Wide DIP
215
215
–40
°
C to +85
°
C
0
°
C to +70
°
C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
TIMING DIAGRAMS
> 5ns
> 50ns
> 50ns
(Load first rank from Data Bus: LDAC = 1)
DB11–DB0
WR
> 50ns
WRITE CYCLE #1
EN
X
t
SETTLING
±1/2LSB
LDAC
WR
> 50ns
> 50ns
V
OUT
WRITE CYCLE #2
(Load second rank from first rank: EN
X
= 1)
±1/2LSB
Reset
> 50ns
+10V
–10V
0V
t
SETTLING
V
OUT
RESET COMMAND (Bipolar Mode)
EN
X
, LDAC, WR = Don’t Care
TRUTH TABLE
WR
EN1
EN2
EN3
EN4
LDAC
RESET
OPERATION
X
1
X
0
0
0
0
0
0
X
X
1
1
1
1
0
1
0
X
X
1
1
1
0
1
1
0
X
X
1
1
0
1
1
1
0
X
X
1
0
1
1
1
1
0
X
X
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
Reset all D/A Latches
No Operation
No Operation
Load Data into First Rank for D/A 4
Load Data into First Rank for D/A 3
Load Data into First Rank for D/A 2
Load Data into First Rank for D/A 1
Load Second Rank from First Rank, All D/As
All Latches Transparent
“X” = Don’t Care