參數(shù)資料
型號: DAC312ER
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 12-Bit High Speed Multiplying D/A Converter
中文描述: PARALLEL, WORD INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, CDIP20
封裝: HREMETIC SEALED, CERDIP-20
文件頁數(shù): 4/14頁
文件大?。?/td> 269K
代理商: DAC312ER
DAC312
–4–
REV. C
WAFER TEST LIMTS
DAC312N
Limit
DAC312G
Limit
Parameter
Symbol
Conditions
Units
Resolution
12
12
Bits min
Monotonicity
12
±
0.05
+10
–5
12
±
0.05
+10
–5
Bits min
Nonlinearity
%FS max
Output Voltage
Compliance
Full-Scale Current
Change <1/2 LSB
V max
V min
Voc
Full-Scale
Current
V
REF
= 10.000 V
R
14
, R
15
= 10.000 k
4.031
3.967
±
1
0.1
±
0.012
±
1/2
0.8
4.063
3.935
±
2
0.1
±
0.025
±
1
0.8
mA max
mA min
μ
A max
μ
A max
%FS max
Bits (LSB) max
Full-Scale Symmetry
I
FSS
I
ZS
DNL
Zero-Scale Current
Differential
Nonlinearity
Deviation from
Ideal Step Size
Logic Input Levels “0”
V
IL
V
IH
V
IS
V
LC
= GND
V
LC
= GND
V max
Logic Input Levels “1”
2
2
V min
Logic Input Swing
+18
–5
+18
–5
V max
V min
Reference Bias
Current
I
15
PSSI
FS+
PSSI
FS–
I+
I–
–2
±
0.001
±
0.001
7
–18
–2
±
0.001
±
0.001
7
–18
μ
A max
Power Supply
Sensitivity
V+ = +13.5 V to +16.5 V, V– = –15 V
V– = –13.5 V to –16.5 V, V+ = +15 V
%/%max
Power Supply
Current
V
S
= +15 V
I
REF
1.0 mA
V
S
= +15 V
I
REF
1.0 mA
mA max
Power
Dissipation
P
D
375
375
mW max
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
@ V
S
=
6
15 V, I
REF
= 1.0 mA, T
A
= 25
8
C, unless otherwse noted. Output characteristics refer to both I
OUT
and I
OUT
.
DICE CHARACT E RIST ICS
DIE SIZE 0.141
×
0.096 inch, 13,536 sq. mils (3.58
×
2.44 mm, 8.74 sq. mm)
1. B1 (MSB)
2. B2
3. B3
4. B4
5. B5
6. B6
7. B7
8. B8
9. B9
10. B10
11. B11
12. B12 (LSB)
13. V
LC
/A
GND
14. V
REF
(+)
15. V
REF
(–)
16. COMP
17. V–
18. I
O
19. I
O
20. V+
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