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參數(shù)資料
| 型號： | DAC312ER |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit High Speed Multiplying D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, CDIP20 |
| 封裝： | HREMETIC SEALED, CERDIP-20 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 269K |
| 代理商： | DAC312ER |
DAC312
–13–
REV. C
DE SCRIPT ION OF OPE RAT ION
T he DAC312 is divided into two major sections, an 8 segment
generator and a 9-bit master/slave D/A converter. In operation
the device performs as follows (see Simplified Schematic).
T he three most significant bits (MSBs) are inputs to a 3-to-8
line decoder. T he selected resistor (R5 in the figure) is con-
nected to the master/slave 9-bit D/A converter. All lower order
resistors (R1 through R4) are summed into the I
O
line, while all
higher order resistors (R6 through R8) are summed into the I
O
line. T he R5 current supplies 512 steps of current (0 mA to
0.499 mA for a 1 mA reference current) which are also summed
into the I
O
or I
O
lines depending on the bits selected. In the fig-
ure, the code selected is: 100 110000000. T herefore, 2 mA (4
×
0.5 mA/segment) +0.375 mA (from master/slave D/A converter)
are summed into I
O
giving an I
O
of 2.375 mA. I
O
has a current
of 1.625 mA with this code. As the three MSB’s are increment-
ed, each successively higher code adds 0.5 mA to I
O
and sub-
tracts 0.5 mA from I
O
, with the selected resistor feeding its
current to the master/slave D/A converter; thus each increment
of the 3 MSBs allows the current in the 9-bit D/A converter to
be added to a pedestal consisting of the sum of all lower order
currents from the segment generator. T his configuration guar-
antees monotonicity.
Expanded Transfer Characteristic Segment (001 010 011)
Simplified Schematic
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| DAC312HR | 制造商:PMI 功能描述: |
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