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參數(shù)資料
| 型號(hào)： | DAC2KY |
| 英文描述： | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 雙通道，12位，125Msps數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 389K |
| 代理商： | DAC2KY |
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DAC2902
SBAS167A
9
FIGURE 1. Block Diagram of the DAC2902.
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC2902 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a full-
scale output current of up to 20mA, as shown in Figure 1. An
internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output
summing node, I
OUT
or I
OUT
. The complementary outputs
deliver a differential output signal, which improves the
dynamic performance through reduction of even-order har-
monics, common-mode signals (noise), and double the peak-
to-peak output signal swing by a factor of two, compared to
single-ended operation.
The segmented architecture results in a significant reduction
of the glitch energy, improves the dynamic performance
(SFDR), and DNL. The current outputs maintain a very high
output impedance of greater than 200ky.
The full-scale output current is determined by the ratio of the
internal reference voltage (approx. +1.25V) and an external
resistor, R
SET
. The resulting I
REF
is internally multiplied by a
factor of 32 to produce an effective DAC output current that
can range from 2mA to 20mA, depending on the value of R
SET
.
The DAC2902 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the cur-
rent source array with its associated switches, and the
reference circuitry.
DAC TRANSFER FUNCTION
Each of the DACs in the DAC2902 has a complementary
current output, I
OUT
1 and I
OUT
2. The full-scale output cur-
rent, I
OUTFS
, is the summation of the two complementary
output currents:
I
OUTFS
= I
OUT
+ I
OUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
I
OUT
= I
OUTFS
(Code/4096)
(2)
I
OUT
= I
OUTFS
(4095 - Code)
(3)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, I
OUTFS
is a function of the refer-
ence current I
REF
, which is determined by the reference
voltage and the external setting resistor, R
SET
.
I
OUTFS
= 32 I
REF
= 32 V
REF
/R
SET
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
V
OUT
= I
OUT
R
LOAD
(5)
V
OUT
= I
OUT
R
LOAD
(6)
DAC
Latch 1
WRT1
CLK1
CLK2
WRT2
Data Input
Port 2
D[11:0]_2
Data Input
Port 1
D[11:0]_1
l
OUT
1
l
OUT
1
Input
Latch 1
Reference
Control Amplifier
FSA2
GSET
PD
REF
IN
FSA1
DAC1
Segmented Switches
Current Sources
DAC2902
l
OUT
2
l
OUT
2
+V
A
+V
D
+V
D
DAC
Latch 2
Input
Latch 2
DAC2
Segmented Switches
Current Sources
AGND
DGND
DGND
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC2902 | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| DAC2902-EVM | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| DAC2900-EVM | DAC2900 10-bit, 125MSPS DC EVM(DAC2900 10位, 125MSPS DC 評(píng)估板) |
| DAC2902-EVM | DAC2902 12-bit, 125MSPS DC EVM(DAC2902 12位, 125MSPS DC 評(píng)估板) |
| DAC2904-EVM | DAC2904 14-bit, 125MSPS DC EVM(DAC2904 14位, 125MSPS DC 評(píng)估板) |
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