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參數(shù)資料
| 型號： | DAC1326X |
| 英文描述： | DAC1326X 1.2V 8BIT 2MSPS DAC|Data Sheet |
| 中文描述： | DAC1326X 1.2V的8位2MSPS援會|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 228K |
| 代理商： | DAC1326X |
SEC ASIC
DAC1350X
10BIT 75MSPS Quad DAC
ANALOG
FUNCTION DESCRIPTION
This is quad 10bit 75MSPS digital to analog
d a t a c o n v e r t e r a n d u s e s c u r re n t - s e g me n t
arc h i t ec t u re fo r 4 -b i t s i n MS B s i d e s an d
binary-weighted architecture for 6-bits in LSB
sides. It contains of 1'st latch block, decoder
block , 2'nd latch block , OPA block , CM
(c u r ren t mi rro r ) b l o ck , BG R ( Ban d Ga p
Reference) block, Auto-load detect block and
analog switch block, etc. This core uses reference
current which deci de the 1LSB current by
dividing the reference current by 32times. So the
reference current must be constant and it can be
constant by using OPA block with high DC gain.
The most significant block of this core is analog
switch block and it must maintain the uniformity
at each switch, so layout designer must care of
it. And more than 90% of
supply current is
dissipated at analog output side. And it uses
samsung standard cell as all digital cell of latch,
decoder and buffer, etc. And to adjust full
current output range, you must decide the Rset
value(connected to IRSET pin) and. Its voltage
o u t p u t c a n b e o b t a i n e d b y c o n n e c t i n g
RL1(connected to IOUT0 pin) and RL2(connected
to IOUT1 pin) ,RL3(connected to IOUT2 pin)
and RL4(connected to IOUT3 pin)
Its maximum
output voltage limit is Compliance voltage. So
you must decide the RL[4:1], VREFOUT and
Rset carefully not to
exceed the output voltage
l i m i t . I t c o n t a i n s P D D A C [ 3 : 0 ] p i n s f o r
power-save of each channel and BGPD for
power-down mode of all blocks. Even though
one or two out of 4 channels enter power-save
mode, the reference block(OPA block,CM block,
BGR block) is st ill alive, but if BGPD is
activated(high), then all blocks of this core is
disable regardless of PDDAC[3:0], so at this case
supply current is almost just about the sum of
leakage. You cant check the BGR's output
v o l t a g e b y c h e c k i n g t h e V R E F O U T p i n .
The user can detect the presence of an expected
load on each DAC output by configuring the
DAC digital inputs such that the detection
comparator
threshold(0.53V)
is
a
useful
threshold for presence of load resistance. Set
DLDSEL[1:0] to select the appropriate DAC
output.
Transition
PRE
to
low,
wait
for
settling DTOUT value and return PRE back to
high.
The IRSET pin creates a +0.7[V] DC reference
that can be forced with an external reference
voltage pin VREFOUT. This voltage when
combined with the external resistor attached to
the IRSET pin sets the output current range
for all quad DACs. The following example
shows how to create a 1Vpk-pk output for a
100 IRE NTSC signal. Any other required
variations can easily be calculated from the
supplied equations. Please remember that these
are ideal equations, the mismatch tolerances
from the data sheet should be taken into
account for any calculations.
The
<figure
1>
diagram
shows
a
typical
relationship between DAC input and voltage
output.
The
<figure
2>
diagram
shows
the
basic
bias-generator and analog current switch.
From this diagram the number of DAC codes
for a 1V delta output is :
C100 = 808 - 10 = 798
1V
808
10
DAC code
Input
An example 10-bit DAC relationship
input code verse output level
<figure 1>
7 / 15
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| DAC1329X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DAC1329X 3.3V 12BIT 80MSPS DAC|Data Sheet |
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