參數(shù)資料
型號： DAC1208D750HN
廠商： NXP SEMICONDUCTORS
元件分類： DAC
英文描述： Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
中文描述： SERIAL INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù)： 64/98頁
文件大小： 554K
代理商： DAC1208D750HN
DAC1208D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 6 December 2010
64 of 98
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
Table 93.
Default settings are shown highlighted.
Bit
Symbol
7 to 6
LANE_SEL_LN3[1:0]
LANE_SELECT register (address 0Eh) bit description
Access
R/W
Value
Description
lane 3 data mapping
ila_in_ln3 = lane_ln0 (dout and controls)
ila_in_ln3 = lane_ln1 (dout and controls)
ila_in_ln3 = lane_ln2 (dout and controls)
ila_in_ln3 = lane_ln3 (dout and controls)
lane 2 data mapping
ila_in_ln2 = lane_ln0 (dout and controls)
ila_in_ln2 = lane_ln1 (dout and controls)
ila_in_ln2 = lane_ln2 (dout and controls)
ila_in_ln2 = lane_ln3 (dout and controls)
lane 1 data mapping
ila_in_ln1 = lane_ln0 (dout and controls)
ila_in_ln1 = lane_ln1 (dout and controls)
ila_in_ln1 = lane_ln2 (dout and controls)
ila_in_ln1 = lane_ln3 (dout and controls
lane 0 data mapping
ila_in_ln0 = lane_ln0 (dout and controls)
ila_in_ln0 = lane_ln1 (dout and controls)
ila_in_ln0 = lane_ln2 (dout and controls)
ila_in_ln0 = lane_ln3 (dout and controls)
00
01
10
11
5 to 4
LANE_SEL_LN2[1:0]
R/W
00
01
10
11
3 to 2
LANE_SEL_LN1[1:0]
R/W
00
01
10
11
1 to 0
LANE_SEL_LN0[1:0]
R/W
00
01
10
11
Table 94.
Bit
3
SOFT_RESET_SCRAMBLER register (address 10h) bit description
Symbol
SR_SCR_LN3
Access
R/W
Value
Description
lane 3 scrambler reset
no action
soft_reset scrambler of lane 3
lane 2 scrambler reset
no action
soft_reset scrambler of lane 2
lane 1 scrambler reset
no action
soft_reset scrambler of lane 1
lane 0 scrambler reset
no action
soft_reset scrambler of lane 0
0
1
2
SR_SCR_LN2
R/W
0
1
1
SR_SCR_LN1
R/W
0
1
0
SR_SCR_LN0
R/W
0
1
Table 95.
Bit
7 to 0
INIT_SCR_S15T8_LN0 register (address 11h) bit description
Symbol
INIT_VALUE_S15_S8_LN0[7:0]
Access
R/W
Value
00h
Description
initialization value for lane 0 descrambler bits
s15 : s8
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DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
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