- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373038 > DAC1208D650HN (NXP Semiconductors N.V.) Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating PDF資料下載
參數(shù)資料
| 型號： | DAC1208D650HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating |
| 封裝： | DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,; |
| 文件頁數(shù)： | 47/98頁 |
| 文件大?。?/td> | 557K |
| 代理商： | DAC1208D650HN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
47 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.15.2.4
Page 1 bit definition detailed description
Please refer to
Table 47
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 48.
Default settings are shown highlighted.
Bit
Symbol
7 to 6
MDS_EQCHECK[1:0]
MDS_MAIN register (address 00h) bit description
Access
R/W
Value
Description
lock mode
lock when (early = 1 and late = 1)
lock when (early = 1 and late = 1 and equal = 1)
lock when equal = 1
force-lock (equal-check = 1)
evaluation restart
no action
transition from 0 to 1 restarts evaluation_counter
NCO synchronization
no action
NCO synchronization enabled
synchronization reference
use lane 1 enable as reference for
synchronization
use lane 2/lane 3 enable as reference for
synchronization
maximum delay
maximum coarse delay is 16T_dclk
maximum coarse delay is 32T_dclk
MDS mode
slave mode
master mode
MDS function
disable MDS function
enable MDS function
00
01
10
11
5
MDS_RUN
R/W
0
1
4
MDS_NCO
R/W
0
1
3
MDS_SEL_LN23
R/W
0
1
2
MDS_32T_ENA
R/W
0
1
1
MDS_MASTER
R/W
0
1
0
MDS_ENA
R/W
0
1
Table 49.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
MDS_WIN_PERIOD_A[7:0]
MDS_WIN_PERIOD_A register (address 01h) bit description
Access
R/W
Value
80h
Description
determines MDS window LOW-time
Table 50.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
MDS_WIN_PERIOD_B[7:0]
MDS_WIN_PERIOD_B register (address 02h) bit description
Access
R/W
Value
40h
Description
determines MDS window HIGH-time
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC1208D750HN | Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating |
| DAC1208D750HN | Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating |
| DL-5538S-C550-SB | 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE |
| DL-5538S-C450-FB | 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE |
| DL-5538S-C450-S | 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1208D650HN/C1,5 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 12BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1208D650HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Bulk |
| DAC1208D650HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Tape and Reel |
| DAC1208D650W1/DB,598 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 DAC DEMOBOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。