參數(shù)資料
型號: DAC1208D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 23/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
23 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.3 Serial Peripheral Interface (SPI)
10.3.1
Protocol description
The DAC1208D650 serial interface is a synchronous serial communication port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that define the operating modes of the chip in both Write mode and Read mode.
This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pin, input and output port respectively). In both
configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with two bytes to five bytes, depending on the content of the
instruction byte (see
Table 8
).
Table 7.
R/W
0
1
In
Table 8
below, N1 and N0 indicate the number of bytes transferred after the instruction
byte.
Table 8.
N1
0
0
1
1
A[4:0] indicates which register is being addressed. In the case of a multiple transfer, this
address points to the first register to be accessed. The address is then internally
decreased after each following data phase.
R/W indicates the mode access, (see
Table 7
).
Fig 13. SPI protocol
001aaj812
RESET_N
SCS_N
SCLK
SDIO
SDO
(optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Read or Write mode access description
Description
Write mode operation
Read mode operation
Number of bytes to be transferred
N0
0
1
0
1
Number of bytes transferred
1
2
3
4
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