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參數(shù)資料
| 型號： | DAC1002LJ |
| 英文描述： | 10-Bit Digital-to-Analog Converter |
| 中文描述： | 10位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 262K |
| 代理商： | DAC1002LJ |
Digital Interface (Continued)
Table III lists the instruction set for the READ mode By the
appropriate setting of the global (G) and address (A1 and
A0) bits one can select a specific DAC to be read or one
can read all the DACs in succession starting with DAC 1
The RF bit determines whether the data changes on the
rising or the falling edge of the system clock With the RF
bit high DO goes out of TRI-STATE on the rising edge that
occurs 1
clock cycles after the end of the instruction byte
the data will continue to be sequentially clocked out by the
following rising clock edges With the RF bit low DO goes
out of TRI-STATE on the falling edge that occurs 1 clock
cycle after the end of the instruction byte the data will con-
tinue to be sequentially clocked by the next falling clock
edges The rising edge of CS returns DO to TRI-STATE
Read back with the RF bit set high is not MICROWIRE
compatible One can choose to read the data back MSB
first or LSB first by setting the ML bit (See
Figures 3 and
4 )
TABLE III READ MODE Instruction Set
SB
RDWR
G
RF
ML
A1
A0
Description
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
1
0
Read DAC 1 LSB first data changes on the falling edge
1
0
1
Read DAC 2 LSB first data changes on the falling edge
1
0
1
0
Read DAC 3 LSB first data changes on the falling edge
1
0
1
Read DAC 4 LSB first data changes on the falling edge
1
0
1
0
Read DAC 1 MSB first data changes on the falling edge
1
0
1
0
1
Read DAC 2 MSB first data changes on the falling edge
1
0
1
0
Read DAC 3 MSB first data changes on the falling edge
1
0
1
Read DAC 4 MSB first data changes on the falling edge
1
0
1
0
Read DAC 1 LSB first data changes on the rising edge
1
0
1
0
1
Read DAC 2 LSB first data changes on the rising edge
1
0
1
0
1
0
Read DAC 3 LSB first data changes on the rising edge
1
0
1
0
1
Read DAC 4 LSB first data changes on the rising edge
1
0
1
0
Read DAC 1 MSB first data changes on the rising edge
1
0
1
0
1
Read DAC 2 MSB first data changes on the rising edge
1
0
1
0
Read DAC 3 MSB first data changes on the rising edge
1
0
1
Read DAC 4 MSB first data changes on the rising edge
1
0
1
0
Read all DACs LSB first data changes on the falling edge
1
0
1
0
Read all DACs MSB first data changes on the falling edge
1
0
1
0
Read all DACs LSB first data changes on the rising edge
1
0
Read all DACs MSB first data changes on the rising edge
Power Fail Function
The DAC1054 powers up with the INT pin in a Low state To
force this output high and reset this flag the CS pin will have
to be brought low When this is done the INT output will be
pulled high again via an external 10 kX pull-up resistor Any-
time a power failure occurs on the DVCC line the INT will be
set low when power is reapplied This feature may be used
by the microprocessor to discard data whose integrity is in
question
Power Supplies
The DAC1054 is designed to operate from a a5V (nominal)
supply There are two supply lines AVCC and DVCC These
pins allow separate external bypass capacitors for the ana-
log and digital portions of the circuit To guarantee accurate
conversions the two supply lines should each be bypassed
with a 01 mF ceramic capacitor in parallel with a 10 mF
tantalum capacitor
11
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