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參數(shù)資料
| 型號(hào)： | D8254 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE INTERVAL TIMER |
| 中文描述： | 可編程間隔計(jì)時(shí)器 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | D8254 |
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
is accomplished by using a CLK input signal
to the D8254 counters which is a derivative of
the system clock source. Another technique
is to externally synchronize the WR and CLK
input signals. This is done by gating WR with
CLK.
Data Bus Buffer
8-bit buffer is used to inter-
face the D8254 to the system bus.
Control Word
- The Control Word Register is
selected by the Read/Write Logic when
ADDR(1:0) = 11. If the CPU then does a write
operation to the D8254, the data is stored in
the Control Word Register and is interpreted
as a Control Word used to define the opera-
tion of the Counters.
C O U N T E R S B L O C K
D I AG R AM
All three Counters (0, 1, 2) are functionally
identical and fully independent. Each can
work as a 16 bit wide Binary or BCD counter,
in one of the six available modes:
●
Interrupt on terminal count
●
Hardware retriggerable One-Shot
●
Rate Generator
●
Square wave mode
●
Software triggered strobe
●
Hardware triggered strobe
The internal block diagram of a single counter
is shown in Figure below.
CRL
CRM
CE
OLL
OLM
Satus
Register
Status
Latch
Ctrl. Word
Register
Control
Unit
clkn
gaten
outn
datao(7:0)
datai(7:0
)
The central element of each Counter is
CE
module
- Counting Element – 16 bit pre-
settable
synchronous
counter.
down
BIN/BCD
Status Register, Status Latch
– Status
register contains actual mode declaration and
value of output signal. Latched in Status
Latch, after receiving Read-Back Command
with STATUS Bit = 0.
Control Unit
– Controls read/write operation
and decrementing of CE.
CR M, CR L
– Input data registers. When
new count is written to counter, the count is
written in the CR and later transferred to CE.
OL L, OL M
– Output data registers. Latched
when the suitable Counter Latch Command is
sent to the D8254.
Control Word
- The Control Word Register is
selected by the Read/Write Logic when
ADDR(1:0) = 11. If the CPU then does a write
operation to the D8254, the data is stored in
the Control Word Register and is interpreted
as a Control Word used to define the opera-
tion of the Counters.
P E R F O R M AN C E
The following table gives a survey about the
Core area and performance in the LATTICE
devices after Place & Route (all key features
have been included):
Device
Speed
grade
-5
-3
-7
LUTs/PFUs
F
max
ispXPGA
ORCA 4
ORCA 3
560 / 173
484 / 116
441 / 105
68 MHz
39 MHz
20 MHz
Core performance in LATTICE devices
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| D82542 | 制造商:Intel 功能描述: |
| D8254-2 | 制造商:Intel 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| D8255 | 制造商:DCD 制造商全稱(chēng):DCD 功能描述:Programmable Peripheral Interface |
| D8255A | 制造商:Rochester Electronics LLC 功能描述: |
| D8255A5 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Peripheral Miscellaneous |
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