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| 型號(hào)： | D8254 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE INTERVAL TIMER |
| 中文描述： | 可編程間隔計(jì)時(shí)器 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 76K |
| 代理商： | D8254 |
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
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use IP Core in unlimited number of FPGA
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within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except
One Year
license where time of
use is limited to 12 months.
●
Single Design license for
○
VHDL, Verilog source code called HDL
Source
○
Encrypted or plain text EDIF called Netlist
●
One Year license for
○
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○
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Upgrade from
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S Y M B O L
datai(7:0)
addr(1:0)
cs
rd
wr
datao(7:0)
out0
clk0
gate0
rst
out1
clk1
gate1
out2
clk2
gate2
P I N S D E S C R I P T I O N
PIN
TYPE
DESCRIPTION
rst
input Global reset
datai(7:0)
input Processor data bus (input)
addr(1:0)
input Processor address lines
cs
input Chip select
rd
input Processor read strobe
wr
input Processor write strobe
clk0
input Clock input for Counter 0
gate0
input Gate input for Counter 0
clk1
input Clock input for Counter 1
gate1
input Gate input for Counter 1
clk2
input Clock input for Counter 2
gate2
input Gate input for Counter 2
datao(7:0) output Processor data bus (output)
out0
output Output of Counter 0
out1
output Output of Counter 1
out2
output Output of Counter 2
B L O C K D I AG R AM
Counter 0
clk0
gate0
out0
Counter 1
Read/Write
Logict
Counter 2
rst
addr(1:0)
wr
rd
cs
Data Bus
Buffer
Control Word
Register
datai(7:0)
datao(7:0)
clk1
gate1
out1
clk1
gate1
out1
Read Write Logic
- The Read/Write Logic
accepts inputs from the system bus and gen-
erates control signals for the other functional
blocks of the D8254. ADDR(1:0) select one of
the three counters or the Control Word Regis-
ter to be read from/written into. A “l(fā)ow'' on the
RD input tells the D8254 that the CPU is
reading one of the counters. A “l(fā)ow'' on the
WR input tells the D8254 that the CPU is writ-
ing either a Control Word or an initial count.
Both RD and WR are qualified by CS; RD
and WR are ignored unless the 82C54 has
been selected by holding CS low. The WR
and CLK signals should be synchronous. This
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相關(guān)代理商/技術(shù)參數(shù) |
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| D82542 | 制造商:Intel 功能描述: |
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