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參數(shù)資料
| 型號： | D6301 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Pentium/SDRAM Clock Generator with Integrated Buffers |
| 中文描述： | 奔騰/ SDRAM時鐘發(fā)生器集成緩沖器 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 52K |
| 代理商： | D6301 |
45437 Warm Springs Blvd., Fre mont, Cali or nia 94539, TEL 510- 492- 0990 FAX 510- 492- 0991
9704.Rev.1C Page 1
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Generates all clock frequencies for Pentium(II), AMD
and Cyrix systemrequiring multiple CPU clocks.
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Supports up to16 Synchronous CPU clocks (4 CPU and
12 SDRAM) and 7 Synchronous PCI BUS clocks.
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Two 14.318Mhz reference clocks and one 2.5V IOAPIC
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One 24Mhz floppy clock and one 48Mhz USB clock.
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Power management control pins to stop CPU, SDRAM
or PCI BUS clocks.
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Supports 2-wire I2C serial bus interface.
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50% duty cycle with low jitter
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Mixed voltage support from3.0 to 5V or (VDDq2=2.5V)
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Available in 300ml 48 pin SSOP.
FEA TURES
PLL52C63-01
Pen ium/S DRAM Clock Gen er ator with In e grated Buff ers
F2
0
0
0
0
1
1
1
1
F1
0
0
1
1
0
0
1
1
F0 PCLK/SDRAM
0
1
0
1
0
1
0
1
BCLK
25
50
41.6
34.2
27.5
37.5
30
33.3
50
100
83.3
68.5
55
75
60
66.6
FRE QUENCY SE LEC TION (MHz)
PIN IN FOR MA TION
BLOCK DIA GRAM
MODE
1 (OUT PUT)
0 (IN PUT)
PIN15
BCLK5
PCISTP
PIN46
REF1
CPUSTP
I/O MODE CON FIGU RA TION
Note
: F2,F1,F0 and MODE are se ecta ble only dur ng power- on. They are
HIGH by de ault and LOW when 10K
Pull down is at ached.
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