參數(shù)資料
型號： D-16
廠商： Texas Instruments, Inc.
英文描述： LOW-POWER DISSIPATION ADSL LINE DRIVER
中文描述： 低功耗ADSL線路驅(qū)動器
文件頁數(shù)： 4/30頁
文件大?。?/td> 1105K
代理商： D-16
www.ti.com
THS6182
SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
R
L
= 100
R
L
= 25
R
L
= 100
R
L
= 25
R
L
= 100
R
L
= 25
V
CC
=
±
5 V
V
CC
=
±
12 V
V
CC
=
±
15 V
V
CC
=
±
12 V
±
3.9
±
3.7
±
10.7
±
10
±
13.5
±
12.7
±
350
±
450
±
450
±
4.1
±
3.9
±
11.0
±
10.6
±
13.9
±
13.4
±
400
±
600
±
600
1000
V
CC
=
±
5 V
V
V
O
Single-ended output voltage swing
V
CC
=
±
12 V
V
V
CC
=
±
15 V
V
R
L
= 5
I
O
Output current
(1)
mA
R
L
= 10
I
(SC)
Short-circuit current
(1)
R
L
= 1
Open-loop
mA
Output resistance
6
k
Output resistance—terminate mode
f = 1 MHz,
Gain = +10
0.05
Output resistance—shutdown mode
f = 1 MHz,
Open-loop
8.5
POWER SUPPLY
Dual supply
±
4
8
±
12
24
±
16.5
V
CC
Operating range
V
Single supply
33
T
A
= 25
°
C
T
A
= full range
T
A
= 25
°
C
T
A
= full range
T
A
= 25
°
C
T
A
= full range
9.7
10.7
V
CC
=
±
5 V
mA
11.7
Quiescent current (each driver)
(2)
Full-bias mode (Bias-1 = 0,
Bias-2 = 0)
(Trimmed with V
CC
=
±
12 V at 25
°
C)
11
12
V
CC
=
±
12 V
mA
12.5
I
CC
11.5
12.5
V
CC
=
±
15 V
mA
13
Mid; Bias-1 - 1, Bias-2 = 0
7.5
8.5
Quiescent current (each driver)
Variable bias modes, V
CC
=
±
12 V
Low; Bias-1 = 0, Bias-2 = 1
4
5
mA
Shutdown; Bias-1 = 1, Bias-2 = 1
0.25
0.9
T
A
= 25
°
C
T
A
= full range
T
A
= 25
°
C
T
A
= full range
-50
-56
V
CC
=
±
5 V,
V
CC
=
±
0.5 V
-47
PSRR
Power supply rejection ratio
dB
-56
-60
V
CC
=
±
12 V,
±
15 V,
V
CC
=
±
1 V
-53
DYNAMIC PERFORMANCE
Gain = +1, RF = 1.2 k
Gain = +2, RF = 1 k
Gain = +5, RF = 1 k
Gain = +10, RF = 1 k
Gain = +1, RF = 1.5 k
Gain = +2, RF = 1 k
Gain = +5, RF = 1 k
Gain = +10, RF = 1 k
Gain = +5
100
80
R
L
= 100
MHz
35
20
Single-ended small-signal bandwidth
(-3 dB), V
O
= 0.1 Vrms
BW
65
60
R
L
= 25
MHz
40
22
SR
Single-ended slew rate
(3)
V
O
= 10 Vpp,
450
V/μs
(1)
A heatsink is required to keep the junction temperature below absolute maximum rating when an output is heavily loaded or shorted.
See Absolute Maximum Ratings section for more information.
Approximately 0.5 mA (total) flows from V
to GND for internal logic control bias.
Slew rate is defined from the 25% to the 75% output levels.
(2)
(3)
4
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