參數(shù)資料
型號(hào)： CYV15G0403TB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Serializer
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 324K
代理商： CYV15G0403TB-BGC
CYV15G0403TB
Document #: 38-02104 Rev. *C
Page 7 of 21
Pin Definitions
CYV15G0403TB Quad HOTLink II Serializer
Name
I/O Characteristics Signal Description
Transmit Path Data and Status Signals
TXDA[9:0]
TXDB[9:0]
TXDC[9:0]
TXDD[9:0]
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
TXERRA
TXERRB
TXERRC
TXERRD
asynchronous to
transmit channel
enable / disable,
asynchronous to
loss or return of
REFCLKx±
LVTTL Input,
synchronous,
sampled by the
Transmit Data Inputs
. TXDx[9:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx latch
via the device configuration interface.
LVTTL Output,
synchronous to
REFCLKx
↑
[3]
,
Transmit Path Error
. TXERRx is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is detected,
TXERRx, for the channel in error, is asserted HIGH and remains asserted until the transmit
Phase-Align Buffer is re-centered with the PABRSTx latch via the device configuration
interface. When TXBISTx = 0, the BIST progress is presented on the associated TXERRx
output. The TXERRx signal pulses HIGH for one transmit-character clock period to
indicate a pass through the BIST sequence once every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
The TXPLL for the associated channel is powered down. This occurs when OE2x and
OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.
The absence of the REFCLKx± signal.
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
REFCLKC±
REFCLKD±
Differential LVPECL
or single-ended
LVTTL input clock
Reference Clock
. REFCLKx± clock inputs are used as the timing references for the
associated transmit PLL. These input clocks may also be selected to clock the transmit
parallel interface. When driven by a single-ended LVCMOS or LVTTL clock source,
connect the clock source to either the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating). When driven by an LVPECL clock source, the
clock must be a differential clock, using both inputs.
Transmit Path Input Clock
. When configuration latch TXCKSELx = 0, the associated
TXCLKx input is selected as the character-rate input clock for the TXDx[9:0] input. In this
mode, the TXCLKx input must be frequency-coherent to its associated TXCLKOx output
clock, but may be offset in phase by any amount. Once initialized, TXCLKx is allowed to
drift in phase as much as ±180 degrees. If the input phase of TXCLKx drifts beyond the
handling capacity of the Phase Align Buffer, TXERRx is asserted to indicate the loss of
data, and remains asserted until the Phase Align Buffer is initialized. The phase of the
TXCLKx input clock relative to its associated REFCLKx± is initialized when the configu-
ration latch PABRSTx is written as 0. When the associated TXERRx is deasserted, the
Phase Align Buffer is initialized and input characters are correctly captured.
Transmit Clock Output
. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or at
twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs have no
fixed phase relationship to REFCLKx±.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input,
internal pull-down
TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD
LVTTL Output
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset
. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW for
a minimum pulse width. When the reset is removed, all state machines, counters and
configuration latches are at an initial state. As per the JTAG specifications the device
RESET cannot reset the JTAG controller. Therefore, the JTAG controller has to be reset
separately. Refer to
“JTAG Support” on page 12
for the methods to reset the JTAG state
machine. See
Table 2 on page 11
for the initialize values of the device configuration
latches.
Notes
2. When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
3. When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
[+] Feedback
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