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參數(shù)資料
| 型號(hào)： | CYV15G0403DXB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256 |
| 文件頁數(shù)： | 18/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYV15G0403DXB-BGXC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 18 of 45
Receive BIST Operation
The receiver channel contains an internal pattern checker that
can be used to validate both device and link operation. These
pattern checkers are enabled by the associated RXBISTx
latch via the device configuration interface. When enabled, a
register in the associated receive channel becomes a
signature pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character or 526-character sequence
that includes all Data and Special Character codes, including
the explicit violation symbols. This provides a predictable yet
pseudo-random sequence that can be matched to an identical
LFSR in the attached Transmitter(s). When synchronized with
the received data stream, the associated Receiver checks
each character in the Decoder with each character generated
by the LFSR and indicates compare errors and BIST status at
the RXSTx[2:0] bits of the Output Register.
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0. This code D0.0 is sent only once per BIST loop. The
status of the BIST progress and any character mismatches are
presented on the RXSTx[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period
per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. These same status values
are presented when the decoder is bypassed and BIST is
enabled on a receive channel.
The specific status reported by the BIST state machine are
listed in
Table 11 on page 25
. These same codes are reported
on the receive status outputs.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In
Self-Test.”
The
sequence
CYP(V)(W)15G0403DXB is identical to that in the CY7B933,
CY7C924DX, and CYP(V)(W)15G0401DXB, allowing interop-
erable systems to be built when used at compatible serial
signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
When the receive paths are configured for REFCLKx±
operation, each pass must be preceded by a 16-character
Word Sync Sequence to allow management of clock
frequency variations.
The receive BIST state machine requires the characters to be
correctly framed for it to detect the BIST sequence. If the Low
Latency Framer is enabled, the Framer misaligns to an aliased
SYNC character within the BIST sequence. If the Alternate
Multi-Byte Framer is enabled and the Receiver outputs are
clocked relative to a recovered clock, it is generally necessary
to frame the receiver before BIST is enabled. If the receive
outputs are clocked relative to REFCLKx±, the transmitter
precedes every 511 character BIST sequence with a 16
character-character Word Sync Sequence.
compared
by
the
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using a clock that is asynchronous in both
frequency and phase from the Elasticity Buffer write clock, or
to be read using a clock that is frequency coherent but with
uncontrolled phase relative to the Elasticity Buffer write clock.
If the chip is configured for operation with a recovered clock,
the Elasticity Buffer is bypassed.
Each Elasticity Buffer is 10 characters deep, and supports and
an 11 bit wide data path. It is capable of supporting a decoded
character and three status bits for each character present in
the buffer. The write clock for these buffers is always the
recovered clock for the associated read channel.
Receive Modes
When the receive channel is clocked by REFCLKx±, the
RXCLKx± outputs present a buffered or divided (depending on
RXRATEx) and delayed form of REFCLKx±. In this mode, the
receive Elasticity Buffers are enabled. For REFCLKx±
clocking, the Elasticity Buffers must be able to insert K28.5
characters and delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
of these insertions and deletions is controlled in part by how
the transmitter sends its data. Insertion of a K28.5 character
can only occur when the receiver has a framing character in
the Elasticity Buffer. Likewise, to delete a framing character,
one must also be in the Elasticity Buffer. To prevent a buffer
overflow or underflow on a receive channel, a minimum
density of framing characters must be present in the received
data streams.
When the receive channel Output Register is clocked by a
recovered clock, no characters are added or deleted and the
receiver Elasticity Buffer is bypassed.
Power Control
The CYP(V)(W)15G0403DXB supports user control of the
powered up or down state of each transmit and receive
channel. The receive channels are controlled by the
RXPLLPDx latch via the device configuration interface. When
RXPLLPDx = 0, the associated PLL and analog circuitry of the
channel is disabled. The transmit channels are controlled by
the OE1x and the OE2x latches via the device configuration
interface. When a driver is disabled via the configuration
interface, it is internally powered down to reduce device power.
If both serial drivers for a channel are in this disabled state, the
associated internal logic for that channel is also powered
down.
Device Reset State
When the CYP(V)(W)15G0403DXB is reset by assertion of
RESET, all state machines, counters, and configuration
latches in the device are initialized to a reset state, and the
Elasticity Buffer pointers are set to a nominal offset.
Additionally, the JTAG controller must also be reset to ensure
valid operation (even if JTAG testing is not performed). See
[+] Feedback
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