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參數(shù)資料
| 型號(hào)： | CYV15G0403DXB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256 |
| 文件頁數(shù)： | 15/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYV15G0403DXB-BGXC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 15 of 45
Each clock multiplier PLL can accept a REFCLKx± input
between 19.5 MHz and 150 MHz (19.5 MHz and 154 MHz for
CYW15G0403DXB), however, this clock range is limited by
the operating mode of the CYP(V)(W)15G0403DXB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.
SPDSELx are 3-level select
[4]
inputs that select one of three
operating ranges for the serial data outputs and inputs of the
associated channel. The operating serial signaling-rate and
allowable range of REFCLKx± frequencies are listed in
Table 4
.
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so it is
necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for transmission lines. These drivers accept data from the
Transmit Shifters. These drivers have signal swings equivalent
to that of standard PECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines. When
configured for local loopback (LPENx = HIGH), all enabled
serial drivers are configured to drive a static differential logic
1. To achieve OBSAI RP3 compliancy, the serial output drivers
must be AC-coupled to the transmission medium.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note
. When a disabled transmit channel (i.e., both outputs
disabled) is re-enabled:
data on the serial outputs may not meet all timing specifi-
cations for up to 250
μ
s
the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
CYP(V)(W)15G0403DXB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
signal of at least VI
DIFF
> 100 mV, or 200 mV peak-to-peak
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal
DC-restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
The local internal loopback (LPENx) allows the serial transmit
data outputs to be routed internally back to the Clock and Data
Recovery circuit associated with each channel. When
configured for local loopback, the associated transmit serial
driver outputs are forced to output a differential logic-1. This
prevents local diagnostic patterns from being broadcast to
attached remote receivers.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
analog amplitude above amplitude level selected by
SDASELx
transition density above the specified limit
range controls report the received data stream inside
normal frequency range (±1500 ppm
[30]
)
receive channel enabled
Presence of reference clock
ULCx is not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the selected
receive interface clock.
Table 4. Operating Speed Settings
SPDSELx
TXRATE
REFCLKx±
Frequency
(MHz)
reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling Rate
(MBaud)
LOW
1
0
1
0
1
0
195–400
MID (Open)
400–800
HIGH
800–1500
(800–1540 for
CYW15G0403DXB)
[+] Feedback
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| CYV15G0403DXB-BGXI | 制造商:Cypress Semiconductor 功能描述: |
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| CYV15G0403TB-BGC | 功能描述:電信線路管理 IC 4x Indep Serializer COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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