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參數(shù)資料
| 型號(hào)： | CYV15G0204RB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 332K |
| 代理商： | CYV15G0204RB-BGXC |
CYV15G0204RB
Document #: 38-02103 Rev. *C
Page 14 of 24
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets both channels. Initialize the JTAG state machine to
its reset state as detailed in
JTAG Support
.
2. Set the static latch banks for the target channel. [Optional
step if the default settings match the desired configuration.]
3. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and set each channel for SMPTE
data reception (RXBISTx[1:0] = 01) or BIST data reception
(RXBISTx[1:0] = 10). [Required step]
JTAG Support
The CYV15G0204RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine should also be
initialized to a reset state. This should be done in addition to
the device reset (using RESET). The JTAG state machine can
be initialized using TRST (asserting it LOW and de-asserting
it or leaving it asserted), or by asserting TMS HIGH for at least
5 consecutive TCLK cycles. This is necessary in order to
ensure that the JTAG controller does not enter any of the test
modes after device power-up. In this JTAG reset state, the rest
of the device will be in normal operation.
Note
. The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0204RB is ‘0C811069’x.
Table 4. Device Control Latch Configuration Table
ADDR
Channel
Type
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
Value
0
(000b)
A
S
1
0
X
X
0
0
RXRATEA
101111
1
(001b)
A
S
SDASEL2A[1]
SDASEL2A[0]
SDASEL1A[1]
SDASEL1A[0]
X
X
TRGRATEA
101011
2
(010b)
A
D
RXBISTA[1]
RXPLLPDA
RXBISTA[0]
X
ROE2A
ROE1A
X
101100
5
(101b)
B
S
1
0
X
X
0
0
RXRATEB
101111
6
(110b)
B
S
SDASEL2B[1]
SDASEL2B[0]
SDASEL1B[1]
SDASEL1B[0]
X
X
TRGRATEB
101011
7
(111b)
B
D
RXBISTB[1]
RXPLLPDB
RXBISTB[0]
X
ROE2B
ROE1B
X
101100
Table 5. Receive BIST Status Bits
{BISTSTx, RXDx[0], RXDx[1]}
Description
Receive BIST Status
(Receive BIST = Enabled)
000, 001
010
011
100
101
BIST Data Compare
. Character compared correctly.
BIST Last Good
. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad
.
Last Character of BIST sequence detected invalid.
BIST Start
. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error
. While comparing characters, a mismatch was found in one or more of the character
bits.
BIST Wait
. The receiver is comparing characters. but has not yet found the start of BIST
character to enable the LFSR.
110
111
[+] Feedback
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