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參數(shù)資料
| 型號： | CYV15G0203TB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Independent Clock Dual HOTLink II Serializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大小： | 525K |
| 代理商： | CYV15G0203TB-BGC |
PRELIMINARY
CYV15G0203TB
Document #: 38-02105 Rev. **
Page 7 of 19
SPDSELA
SPDSELB
3-Level Select
[4]
static control input
Serial Rate Select
. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s PLL.
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
ADDR[2:0]
LVTTL input
asynchronous,
internal pull-up
the latch specified by the address location on the ADDR[2:0] bus.
[5]
Table 2
lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET.
Table 3
shows how the latches are mapped in the device.
DATA[3:0]
LVTTL input
asynchronous,
internal pull-up
specified by address location on the ADDR[2:0] bus.
[5 ]
Table 2
lists the configuration
latches within the device, and the initialization value of the latches upon the assertion
of RESET.
Table 3
shows how the latches are mapped in the device.
Internal Device Configuration Latches
TXCKSEL[A..B]
Internal Latch
[6]
Transmit Clock Select
.
TXRATE[A..B]
Internal Latch
[6]
Transmit PLL Clock Rate Select
.
TXBIST[A..B]
Internal Latch
[6]
Transmit Bist Disabled
.
OE2[A..B]
Internal Latch
[6]
Differential Serial Output Driver 2 Enable
.
OE1[A..B]
Internal Latch
[6]
Differential Serial Output Driver 1 Enable
.
PABRST[A..B]
Internal Latch
[6]
Transmit Clock Phase Alignment Buffer Reset
.
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
NO CONNECT, or GND only.
Analog I/O
OUTA1±
OUTB1±
Output
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-
compatible connections.
OUTA2±
OUTB2±
Output
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Control Write Enable
. The WREN input writes the values of the DATA[3:0] bus into
the latch specified by the address location on the ADDR[2:0] bus.
[5]
Control Addressing Bus
. The ADDR[2:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[3:0] bus into
Control Data Bus
. The DATA[3:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[3:0] bus into the latch
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a
CML Differential
Primary Differential Serial Data Output
. The OUTx1± PECL-compatible CML
CML Differential
Secondary Differential Serial Data Output
. The OUTx2± PECL-compatible CML
Notes:
4.
3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
See
Device Configuration and Control Interface
for detailed information on the operation of the Configuration Interface.
See
Device Configuration and Control Interface
for detailed information on the internal latches.
5.
6.
Pin Definitions
(continued)
CYV15G0203TB Dual HOTLink II Serializer
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0204RB | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGXC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204TRB | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0203TB-BGXC | 功能描述:視頻 IC 2x Indep Serializers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
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