參數(shù)資料
型號(hào)： CYV15G0203TB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Dual HOTLink II Serializer
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256
文件頁(yè)數(shù)： 10/19頁(yè)
文件大?。?/td> 525K
代理商： CYV15G0203TB-BGC
PRELIMINARY
CYV15G0203TB
Document #: 38-02105 Rev. **
Page 10 of 19
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets both channels.
2. Set the static latch banks for the target channel.
3. Set the dynamic bank of latches for the target channel.
Enable the output drivers. [Required step.]
4. Reset the Phase Alignment Buffer for the target channel.
[Optional if phase align buffer is bypassed.]
JTAG Support
The CYV15G0203TB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0203TB is ‘0C810069’x.
TXBISTA
TXBISTB
Transmit Bist Disabled
. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When
TXBISTx = 0, the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable
. The initialization value of the OE2x latch =
0. OE2x selects if the OUT2x± secondary differential output drivers are enabled or disabled. When OE2x
= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled
via the configuration interface, it is internally powered down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable
. The initialization value of the OE1x latch = 0.
OE1x selects if the OUT1x± primary differential output drivers are enabled or disabled. When OE1x =
1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled
via the configuration interface, it is internally powered down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx
is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx
↑
to synchronize it to the internal
clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
OE2A
OE2B
OE1A
OE1B
PABRSTA
PABRSTB
Table 2. Device Configuration and Control Latch Descriptions
(continued)
Table 3. Device Control Latch Configuration Table
ADDR
0
(000b)
1
(001b)
2
(010b)
9
(101b)
10
(110b)
11
(111b)
Channel
A
Type
S
DATA3
X
DATA2
X
DATA1
0
DATA0
X
Reset
Value
1111
A
S
X
0
TXCKSELA
TXRATEA
0110
A
D
TXBISTA
OE2A
OE1A
PABRSTA
1001
B
S
X
X
0
X
1111
B
S
X
0
TXCKSELB
TXRATEB
0110
B
D
TXBISTB
OE2B
OE1B
PABRSTB
1001
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