參數(shù)資料
型號: CYV15G0203TB_07
廠商: Cypress Semiconductor Corp.
英文描述: Independent Clock Dual HOTLink II⑩ Serializer
中文描述: 獨(dú)立時(shí)鐘雙串行器的HOTLink二⑩
文件頁數(shù): 13/20頁
文件大?。?/td> 307K
代理商: CYV15G0203TB_07
CYV15G0203TB
Document #: 38-02105 Rev. *C
Page 13 of 20
AC Test Loads and Waveforms
CYV15G0203TB AC Electrical Characteristics
V
OLC
Output LOW Voltage
(V
CC
Referenced)
100
Ω
differential load
150
Ω
differential load
100
Ω
differential load
150
Ω
differential load
V
CC
– 1.4
V
CC
– 1.4
450
560
Typ.
435
V
CC
– 0.7
V
CC
– 0.7
900
1000
Max.
530
V
V
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
mV
mV
Power Supply
I
CC [10,11]
Max Power Supply Current
REFCLKx =
MAX
REFCLKx =
125 MHz
Commercial
mA
I
CC [10,11]
Typical Power Supply Current
Commercial
425
520
mA
CYV15G0203TB DC Electrical Characteristics
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
270 ps
270 ps
[13]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
Ω
R2 = 435
Ω
C
L
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
Ω
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
1 ns
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[12]
[12]
Parameter
CYV15G0203TB Transmitter LVTTL Switching Characteristics
Over the Operating Range
f
TS
TXCLKx Clock Cycle Frequency
t
TXCLK
TXCLKx Period=1/f
TS
t
TXCLKH[14]
TXCLKx HIGH Time
t
TXCLKL[14]
TXCLKx LOW Time
t
TXCLKR [14, 15, 16, 17]
TXCLKx Rise Time
t
TXCLKF [14, 15, 16, 17]
TXCLKx Fall Time
t
TXDS
Transmit Data Set-up Time to
TXCLKx
(TXCKSELx
=
0)
t
TXDH
Transmit Data Hold Time from TXCLKx
(TXCKSELx
=
0)
f
TOS
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
t
TXCLKO
TXCLKOx Period = 1/f
TOS
t
TXCLKOD
TXCLKO Duty Cycle centered at 60% HIGH time
Notes
10.Maximum I
is measured with V
CC
= MAX, T
A
= 25°C, with both channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
11. Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C, with both channels enabled and one Serial Line Driver per channel sending
a continuous alternating 01 pattern. The redundant outputs on each channel are powered down.
12.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
14.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15.The ratio of rise time to falling time must not vary by greater than 2:1.
16.For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
17.All transmit AC timing parameters measured with 1 ns typical rise time and fall time.
Description
Min.
Max.
Unit
19.5
6.66
2.2
2.2
0.2
0.2
2.2
1.0
19.5
6.66
–1.9
150
51.28
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
1.7
1.7
150
51.28
0
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