- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380227 > CYV15G0203TB_07 (Cypress Semiconductor Corp.) Independent Clock Dual HOTLink II⑩ Serializer PDF資料下載
參數(shù)資料
| 型號： | CYV15G0203TB_07 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Serializer |
| 中文描述： | 獨立時鐘雙串行器的HOTLink二⑩ |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 307K |
| 代理商： | CYV15G0203TB_07 |
CYV15G0203TB
Document #: 38-02105 Rev. *C
Page 10 of 20
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets both channels. Initialize the JTAG state machine to
its reset state as detailed in the
JTAG Support
section.
2. Set the static latch banks for the target channel.
3. Set the dynamic bank of latches for the target channel.
Enable the output drivers. [Required step.]
4. Reset the Phase Alignment Buffer for the target channel.
[Optional if phase align buffer is bypassed.]
JTAG Support
The CYV15G0203TB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain. To ensure valid
device operation after power-up (including non-JTAG
operation), the JTAG state machine should also be initialized
to a reset state. This should be done in addition to the device
reset (using RESET). The JTAG state machine can be
initialized using TRST (asserting it LOW and de-asserting it or
leaving it asserted), or by asserting TMS HIGH for at least 5
consecutive TCLK cycles. This is necessary in order to ensure
that the JTAG controller does not enter any of the test modes
after device power-up. In this JTAG reset state, the rest of the
device will be in normal operation.
Note
. The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
Table 2. Device Configuration and Control Latch Descriptions
Name
TXCKSELA
TXCKSELB
Signal Description
Transmit Clock Select
. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input
register TXDx[9:0] is clocked by REFCLKx
↑.
In this mode, the phase alignment buffer is bypassed. When
TXCKSELx = 0, the associated TXCLKx
↑
is used to clock in the input register TXDx[9:0].
Transmit PLL Clock Rate Select
. The initialization value of the TXRATEx latch = 0. TXRATEx is used
to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the
TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated
REFCLKx± input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by
20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the
frequency rate of the REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data
Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx =
LOW, is an invalid state and this combination is reserved.
Transmit Bist Disabled
. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When
TXBISTx = 0, the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable
. The initialization value of the OE2x latch =
0. OE2x selects if the OUT2x± secondary differential output drivers are enabled or disabled. When OE2x
= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via
the configuration interface, it is internally powered down to reduce device power. If both serial drivers for
a channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable
. The initialization value of the OE1x latch = 0.
OE1x selects if the OUT1x± primary differential output drivers are enabled or disabled. When OE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx
is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx
↑
to synchronize it to the internal
clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
TXRATEA
TXRATEB
TXBISTA
TXBISTB
OE2A
OE2B
OE1A
OE1B
PABRSTA
PABRSTB
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CYV15G0203TB-BGXC | Independent Clock Dual HOTLink II⑩ Serializer |
| CYV15G0203TB | Independent Clock Dual HOTLink II Serializer |
| CYV15G0203TB-BGC | Independent Clock Dual HOTLink II Serializer |
| CYV15G0204RB | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0203TB-BGC | 功能描述:電信線路管理 IC 2x Indep Serializers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0203TB-BGXC | 功能描述:視頻 IC 2x Indep Serializers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。