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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 28 of 45
Differential CML Serial Outputs: OUTA1
±
, OUTA2
±
, OUTB1
±
, OUTB2
±,
OUTC1
±
, OUTC2
±
, OUTD1
±
, OUTD2
±
V
OHC
Output HIGH Voltage
(V
cc
Referenced)
100
Ω
differential load
150
Ω
differential load
100
Ω
differential load
150
Ω
differential load
100
Ω
differential load
150
Ω
differential load
V
CC
– 0.5
V
CC
– 0.5
V
CC
– 1.4
V
CC
– 1.4
450
560
V
CC
– 0.2
V
CC
– 0.2
V
CC
– 0.7
V
CC
– 0.7
900
1000
V
V
V
V
V
OLC
Output LOW Voltage
(V
CC
Referenced)
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
mV
mV
Differential Serial Line Receiver Inputs: INA1
±
, INA2
±
, INB1
±
, INB2
±
, INC1
±
, INC2
±
, IND1
±
, IND2
±
V
DIFFs[11]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
VI
COM[13]
Common Mode input range
100
1200
V
CC
mV
V
V
μ
A
μ
A
V
V
CC
– 2.0
V
IN
= V
IHE
Max.
V
IN
= V
ILE
Min.
((V
CC
– 2.0V)+0.5)min,
(V
CC
– 0.5V) max.
1350
–700
+1.25
+3.1
Power Supply
I
CC [14, 15]
Typ.
910
Max.
1270
1320
1270
1320
Max Power Supply Current
REFCLKx =
MAX
Commercial
Industrial
Commercial
Industrial
mA
mA
mA
mA
I
CC [14, 15]
Typical Power Supply Current
REFCLKx =
125 MHz
900
CYP(V)(W)15G0403DXB DC Electrical Characteristics
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Notes
13.The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
14.Maximum I
is measured with V
CC
= MAX, RFENx = 0, T
A
= 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01
pattern, and outputs unloaded.
15.Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C, RFENx = 0, with all channels enabled and one Serial Line Driver per transmit
channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
16.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
17.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
AC Test Loads and Waveforms
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
≤
270 ps
≤
270 ps
[17]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
Ω
R2 = 435
Ω
C
L
≤
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
Ω
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
≤
1 ns
≤
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[16]
[16]
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